Il 23/11/23 12:02, Michael Walle ha scritto:
The lowest supported clock frequency of the PHY is 125MHz (see also mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the wrong minimal value, which will make the .enable() op return -EINVAL on low frequencies. Fix the minimal clamping value.Fixes: efda51a58b4a ("drm/mediatek: add mipi_tx driver for mt8183") Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
