Vinay Belgaumkar <[email protected]> writes: > This bit does not cause an explicit L3 flush. We already use > PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose. > > Cc: Nirmoy Das <[email protected]> > Cc: Mikka Kuoppala <[email protected]> s/kk/k
> Signed-off-by: Vinay Belgaumkar <[email protected]> > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index ba4c2422b340..abbc02f3e66e 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -247,6 +247,7 @@ static int mtl_dummy_pipe_control(struct i915_request *rq) > int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > { > struct intel_engine_cs *engine = rq->engine; > + struct intel_gt *gt = rq->engine->gt; > > /* > * On Aux CCS platforms the invalidation of the Aux > @@ -278,7 +279,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 > mode) > * deals with Protected Memory which is not needed for > * AUX CCS invalidation and lead to unwanted side effects. > */ > - if (mode & EMIT_FLUSH) > + if ((mode & EMIT_FLUSH) && > + !(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))) > bit_group_1 |= PIPE_CONTROL_FLUSH_L3; Yes its best to apply for MTL first. Acked-by: Mika Kuoppala <[email protected]< > > bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; > @@ -812,12 +814,14 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request > *rq, u32 *cs) > u32 flags = (PIPE_CONTROL_CS_STALL | > PIPE_CONTROL_TLB_INVALIDATE | > PIPE_CONTROL_TILE_CACHE_FLUSH | > - PIPE_CONTROL_FLUSH_L3 | > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > PIPE_CONTROL_DEPTH_CACHE_FLUSH | > PIPE_CONTROL_DC_FLUSH_ENABLE | > PIPE_CONTROL_FLUSH_ENABLE); > > + if (!(IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))) > + flags |= PIPE_CONTROL_FLUSH_L3; > + > /* Wa_14016712196 */ > if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || > IS_DG2(i915)) > /* dummy PIPE_CONTROL + depth flush */ > -- > 2.38.1
