On Fri, 18 Aug 2023, Deucher, Alexander wrote: > [Public] > > > -----Original Message----- > > From: Ilpo Järvinen <[email protected]> > > Sent: Monday, July 17, 2023 8:05 AM > > To: [email protected]; Bjorn Helgaas <[email protected]>; Lorenzo > > Pieralisi <[email protected]>; Rob Herring <[email protected]>; > > Krzysztof Wilczyński <[email protected]>; Emmanuel Grumbach > > <[email protected]>; Rafael J . Wysocki <[email protected]>; > > Heiner Kallweit <[email protected]>; Lukas Wunner <[email protected]>; > > Andy Shevchenko <[email protected]>; Deucher, Alexander > > <[email protected]>; Koenig, Christian > > <[email protected]>; Pan, Xinhui <[email protected]>; David > > Airlie <[email protected]>; Daniel Vetter <[email protected]>; amd- > > [email protected]; [email protected]; linux- > > [email protected] > > Cc: Dean Luick <[email protected]>; Jonas Dreßler > > <[email protected]>; Ilpo Järvinen <[email protected]>; > > [email protected] > > Subject: [PATCH v5 06/11] drm/radeon: Use RMW accessors for changing > > LNKCTL > > > > Don't assume that only the driver would be accessing LNKCTL. ASPM policy > > changes can trigger write to LNKCTL outside of driver's control. > > And in the case of upstream bridge, the driver does not even own the device > > it's changing the registers for. > > > > Use RMW capability accessors which do proper locking to avoid losing > > concurrent updates to the register value. > > > > Fixes: 8a7cd27679d0 ("drm/radeon/cik: add support for pcie gen1/2/3 > > switching") > > Fixes: b9d305dfb66c ("drm/radeon: implement pcie gen2/3 support for SI") > > Suggested-by: Lukas Wunner <[email protected]> > > Signed-off-by: Ilpo Järvinen <[email protected]> > > Cc: [email protected] > > For this and the amdgpu patch: > Acked-by: Alex Deucher <[email protected]> > I'm not sure if this is stable material however. Is there some issue today?
These were added without Cc stable into pci.git/pcie-rmw. -- i.
