RV1126 MIPI DSI supports V1.2 DPHY with 4 lanes and 1Gbps transfer rate for lane.
Add support for it. Signed-off-by: Jagan Teki <[email protected]> --- Cc: [email protected] Cc: Sandy Huang <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 0100162a73b2..8bafb2a2747f 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -198,6 +198,11 @@ #define RK3568_DSI1_TURNDISABLE BIT(2) #define RK3568_DSI1_FORCERXMODE BIT(0) +#define RV1126_GRF_DSIPHY_CON 0x10220 +#define RV1126_DSI_FORCETXSTOPMODE (0xf << 4) +#define RV1126_DSI_TURNDISABLE BIT(2) +#define RV1126_DSI_FORCERXMODE BIT(0) + #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) enum { @@ -1651,6 +1656,18 @@ static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rv1126_chip_data[] = { + { + .reg = 0xffb30000, + .lanecfg1_grf_reg = RV1126_GRF_DSIPHY_CON, + .lanecfg1 = HIWORD_UPDATE(0, RV1126_DSI_TURNDISABLE | + RV1126_DSI_FORCERXMODE | + RV1126_DSI_FORCETXSTOPMODE), + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { { .compatible = "rockchip,px30-mipi-dsi", @@ -1664,6 +1681,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = &rk3568_chip_data, + }, { + .compatible = "rockchip,rv1126-mipi-dsi", + .data = &rv1126_chip_data, }, { /* sentinel */ } }; -- 2.25.1
