On 7/17/2023 2:51 PM, Andi Shyti wrote:
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Signed-off-by: Andi Shyti <[email protected]>
Cc: Jonathan Cavitt <[email protected]>
Cc: Nirmoy Das <[email protected]>
Cc: <[email protected]> # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 12 +++++++++++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index bee3b7dc595cf..04484385189ad 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -207,7 +207,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
* memory traffic is quiesced prior.
*/
if ((mode & EMIT_INVALIDATE) && !HAS_FLAT_CCS(engine->i915))
- mode |= EMIT_FLUSH;
+ mode |= EMIT_FLUSH | EMIT_CCS_FLUSH;
if (mode & EMIT_FLUSH) {
u32 flags = 0;
@@ -232,6 +232,16 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
+ /*
+ * When required, in MTL+ platforms, in the render and compute
+ * engines we need to set the CCS_FLUSH bit in the pipe control
+ */
+ if (mode & EMIT_CCS_FLUSH &&
+ GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
+ (engine->class == RENDER_CLASS ||
+ engine->class == COMPUTE_CLASS))
PIPE_CONTROL is only available for render and compute so we can skip
this engine check.
+ flags |= PIPE_CONTROL_CCS_FLUSH;
This "flags" is applied to DWORD 1 of PIPE_CONTROL but we need this for
DWORD 0
Regards,
Nirmoy
+
if (!HAS_3D_PIPELINE(engine->i915))
flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
else if (engine->class == COMPUTE_CLASS)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index e99a6fa03d453..e2cae9d02bd62 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -514,6 +514,7 @@ struct intel_engine_cs {
int (*emit_flush)(struct i915_request *request, u32 mode);
#define EMIT_INVALIDATE BIT(0)
#define EMIT_FLUSH BIT(1)
+#define EMIT_CCS_FLUSH BIT(2) /* MTL+ */
#define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
int (*emit_bb_start)(struct i915_request *rq,
u64 offset, u32 length,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 5d143e2a8db03..5df7cce23197c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -299,6 +299,7 @@
#define PIPE_CONTROL_QW_WRITE (1<<14)
#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
#define PIPE_CONTROL_DEPTH_STALL (1<<13)
+#define PIPE_CONTROL_CCS_FLUSH (1<<13) /* MTL+ */
#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
