On 6/2/23 21:15, Lucas Stach wrote:
From: David Jander <[email protected]>
The PLL often fails to lock with this delay. The new value was
determined by trial and error increasing the delay bit by bit
until the error did not occurr anymore even after several tries.
Then double that value was taken as the minimum delay to be safe.
Signed-off-by: David Jander <[email protected]>
Signed-off-by: Lucas Stach <[email protected]>
Tested-by: Marek Vasut <[email protected]> # TC9595
Reviewed-by: Marek Vasut <[email protected]>
