On Mon, May 29, 2023 at 03:52:27PM +0200, Konrad Dybcio wrote: > > Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also > need REG_A6XX_GBIF_HALT to be set to 0. > > This is typically done automatically on successful GX collapse, but in > case that fails, we should take care of it. > > Also, add a memory barrier to ensure it's gone through before jumping > to further initialization. > > Reviewed-by: Dmitry Baryshkov <[email protected]> > Signed-off-by: Konrad Dybcio <[email protected]> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 083ccb5bcb4e..dfde5fb65eed 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1003,8 +1003,12 @@ static int hw_init(struct msm_gpu *gpu) > a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); > > /* Clear GBIF halt in case GX domain was not collapsed */ > - if (a6xx_has_gbif(adreno_gpu)) > + if (a6xx_has_gbif(adreno_gpu)) { > + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); > gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); > + /* Let's make extra sure that the GPU can access the memory.. */ > + mb(); This barrier is unnecessary because writel transactions are ordered and we don't expect a traffic from GPU immediately after this.
-Akhil > + } > > gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); > > > -- > 2.40.1 >
