On 26.01.2023 16:16, Konrad Dybcio wrote: > Currently we only utilize the OPP table connected to the GPU for > getting (available) frequencies. We do however need to scale the > voltage rail(s) accordingly to ensure that we aren't trying to > run the GPU at 1GHz with a VDD_LOW vote, as that would result in > an otherwise inexplainable hang. > > Tell the OPP framework that we want to scale the "core" clock > and swap out the clk_set_rate to a dev_pm_opp_set_rate in > msm_devfreq_target() to enable usage of required-opps and by > extension proper voltage level/corner scaling. > > Signed-off-by: Konrad Dybcio <[email protected]> > --- Welp, as-is, this breaks devfreq on GPUs with a GMU.. Will fix.. Konrad > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ > drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index 817599766329..c85ae3845a4e 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -1047,6 +1047,9 @@ int adreno_gpu_init(struct drm_device *drm, struct > platform_device *pdev, > const char *gpu_name; > u32 speedbin; > > + /* This can only be done here, or devm_pm_opp_set_supported_hw will > WARN_ON() */ > + devm_pm_opp_set_clkname(dev, "core"); > + > adreno_gpu->funcs = funcs; > adreno_gpu->info = adreno_info(config->rev); > adreno_gpu->gmem = adreno_gpu->info->gmem; > diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c > b/drivers/gpu/drm/msm/msm_gpu_devfreq.c > index e27dbf12b5e8..ea70c1c32d94 100644 > --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c > +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c > @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned > long *freq, > gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); > mutex_unlock(&df->lock); > } else { > - clk_set_rate(gpu->core_clk, *freq); > + dev_pm_opp_set_rate(dev, *freq); > } > > dev_pm_opp_put(opp);
