Hi,
On 06/07/2022 15:34, Robert Foss wrote:
On Fri, 1 Jul 2022 at 13:00, Marek Vasut <[email protected]> wrote:
On 7/1/22 08:56, Liu Ying wrote:
With LVDS dual link, up to 160MHz mode clock rate is supported.
With LVDS single link, up to 80MHz mode clock rate is supported.
Fix mode clock rate validation by swapping the maximum mode clock
rates of the two link modes.
Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB
bridge")
Cc: Andrzej Hajda <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Robert Foss <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: Jonas Karlman <[email protected]>
Cc: Jernej Skrabec <[email protected]>
Cc: David Airlie <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Sam Ravnborg <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: NXP Linux Team <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Applied 1-2/3 to drm-misc-next. Picked Mareks patch for 3/3 since it
was submitted first and is identical.
Seems we'll have a conflict when drm-misc-fixes is backmerged in drm-misc-next !
Neil
