On 12/18/21 10:50 PM, Antonio Borneo wrote:
The dsi has several constraints on the video modes it can support, mainly due to the frequencies that can be generated by the PLL integrated in the DSI device. Verify that the required HS clock can be generated by the PLL. The dsi clock from the dsi PLL and the ltdc pixel clock are asynchronous. The dsi needs to return in LP mode during HFP or HBP to re-synchronize at each video line. Verify that the duration of HFP and HBP allows the dsi to enter in LP mode. Signed-off-by: Antonio Borneo <[email protected]> --- To: David Airlie <[email protected]> To: Daniel Vetter <[email protected]> To: Andrzej Hajda <[email protected]> To: Neil Armstrong <[email protected]> To: Robert Foss <[email protected]> To: Laurent Pinchart <[email protected]> To: Jonas Karlman <[email protected]> To: Jernej Skrabec <[email protected]> To: Yannick Fertre <[email protected]> To: Philippe Cornu <[email protected]> To: Benjamin Gaignard <[email protected]> To: Maxime Coquelin <[email protected]> To: Alexandre Torgue <[email protected]> To: Philipp Zabel <[email protected]> To: [email protected] To: [email protected] To: [email protected] Cc: [email protected] --- drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 98 +++++++++++++++++++++++++++ 1 file changed, 98 insertions(+)
Hi Antonio, many thanks for your patch. Nice improvement for better filtering supported modes... Acked-by: Philippe Cornu <[email protected]> Reviewed-by: Philippe Cornu <[email protected]> Philippe :-)
