Hi Matt, On Thu, Oct 28, 2021 at 08:28:10PM -0700, Matt Roper wrote: > On a multi-tile platform, each tile has its own registers + GGTT space, > and BAR 0 is extended to cover all of them. Upcoming patches will start > exposing the tiles as multiple GTs within a single PCI device. In > preparation for supporting such setups, restructure the driver's probe > code a bit. > > Only the primary/root tile is initialized for now; the other tiles will > be detected and plugged in by future patches once the necessary > infrastructure is in place to handle them. > > v2: > - Rename for naming prefix consistency. (Jani, Lucas) > > Original-author: Abdiel Janulgue > Cc: Daniele Ceraolo Spurio <[email protected]> > Cc: Matthew Auld <[email protected]> > Cc: Joonas Lahtinen <[email protected]> > Cc: Lucas De Marchi <[email protected]> > Cc: Jani Nikula <[email protected]> > Signed-off-by: Daniele Ceraolo Spurio <[email protected]> > Signed-off-by: Tvrtko Ursulin <[email protected]> > Signed-off-by: Matt Roper <[email protected]>
Looks correct to me: Reviewed-by: Andi Shyti <[email protected]> Andi
