Am Montag, dem 21.06.2021 um 00:49 +0200 schrieb Marek Vasut:
> Make sure the FIFO_CLEAR bit is latched in when configuring the
> controller, so that the FIFO is really cleared. And then clear
> the FIFO_CLEAR bit, since it is not self-clearing.
>
> Fixes: 45d59d704080 ("drm: Add new driver for MXSFB controller")
> Signed-off-by: Marek Vasut <[email protected]>
> Cc: Daniel Abrecht <[email protected]>
> Cc: Emil Velikov <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Cc: Lucas Stach <[email protected]>
> Cc: Stefan Agner <[email protected]>
> ---
> drivers/gpu/drm/mxsfb/mxsfb_kms.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
> b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
> index 98d8ba0bae84..22cb749fc9bc 100644
> --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
> +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
> @@ -241,6 +241,9 @@ static void mxsfb_crtc_mode_set_nofb(struct
> mxsfb_drm_private *mxsfb,
>
> /* Clear the FIFOs */
> writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
> + readl(mxsfb->base + LCDC_CTRL1);
Do you really need those readbacks? As both writes are targeting the
same slave interface, the memory barrier in the clear write should push
the set write.
> + writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR);
> + readl(mxsfb->base + LCDC_CTRL1);
>
> if (mxsfb->devdata->has_overlay)
> writel(0, mxsfb->base + LCDC_AS_CTRL);
