Applied. Thanks!
On Thu, May 20, 2021 at 8:03 AM Lee Jones <[email protected]> wrote: > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1008:5: warning: no previous > prototype for ‘gfx_v9_4_2_query_ras_error_count’ [-Wmissing-prototypes] > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1054:6: warning: no previous > prototype for ‘gfx_v9_4_2_reset_ras_error_count’ [-Wmissing-prototypes] > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1063:5: warning: no previous > prototype for ‘gfx_v9_4_2_ras_error_inject’ [-Wmissing-prototypes] > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1133:6: warning: no previous > prototype for ‘gfx_v9_4_2_query_ras_error_status’ [-Wmissing-prototypes] > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1143:6: warning: no previous > prototype for ‘gfx_v9_4_2_reset_ras_error_status’ [-Wmissing-prototypes] > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c:1153:6: warning: no previous > prototype for ‘gfx_v9_4_2_enable_watchdog_timer’ [-Wmissing-prototypes] > > Cc: Alex Deucher <[email protected]> > Cc: "Christian König" <[email protected]> > Cc: David Airlie <[email protected]> > Cc: Daniel Vetter <[email protected]> > Cc: [email protected] > Cc: [email protected] > Signed-off-by: Lee Jones <[email protected]> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c > index dbad9ef002d59..87ec96a18a5dd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c > @@ -1641,8 +1641,8 @@ static int gfx_v9_4_2_query_utc_edc_count(struct > amdgpu_device *adev, > return 0; > } > > -int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, > - void *ras_error_status) > +static int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, > + void *ras_error_status) > { > struct ras_err_data *err_data = (struct ras_err_data > *)ras_error_status; > uint32_t sec_count = 0, ded_count = 0; > @@ -1690,7 +1690,7 @@ static void gfx_v9_4_2_reset_ea_err_status(struct > amdgpu_device *adev) > mutex_unlock(&adev->grbm_idx_mutex); > } > > -void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev) > +static void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev) > { > if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) > return; > @@ -1699,7 +1699,7 @@ void gfx_v9_4_2_reset_ras_error_count(struct > amdgpu_device *adev) > gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL); > } > > -int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if) > +static int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void > *inject_if) > { > struct ras_inject_if *info = (struct ras_inject_if *)inject_if; > int ret; > @@ -1772,7 +1772,7 @@ static void gfx_v9_4_2_query_utc_err_status(struct > amdgpu_device *adev) > } > } > > -void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev) > +static void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev) > { > if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) > return; > @@ -1782,7 +1782,7 @@ void gfx_v9_4_2_query_ras_error_status(struct > amdgpu_device *adev) > gfx_v9_4_2_query_sq_timeout_status(adev); > } > > -void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev) > +static void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev) > { > if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) > return; > @@ -1792,7 +1792,7 @@ void gfx_v9_4_2_reset_ras_error_status(struct > amdgpu_device *adev) > gfx_v9_4_2_reset_sq_timeout_status(adev); > } > > -void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev) > +static void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev) > { > uint32_t i; > uint32_t data; > -- > 2.31.1 >
