The check on unchanged HS clock rate in ->mode_set() improves the callback's performance a bit by early return. However, the up-coming patch would get MIPI DSI controller and PHY ready in ->mode_set() after that check, thus likely skipped. So, this patch removes that check to make sure MIPI DSI controller and PHY will be brought up and taken down from ->mode_set() and ->atomic_disable() respectively in pairs.
Cc: Andrzej Hajda <[email protected]> Cc: Neil Armstrong <[email protected]> Cc: Robert Foss <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Jonas Karlman <[email protected]> Cc: Jernej Skrabec <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Guido Günther <[email protected]> Cc: Robert Chiras <[email protected]> Cc: NXP Linux Team <[email protected]> Signed-off-by: Liu Ying <[email protected]> --- v2->v3: * Split from the single patch in v2 to clarify changes. (Neil) drivers/gpu/drm/bridge/nwl-dsi.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index c65ca860712d2..601ccc4a7cdc7 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -856,13 +856,6 @@ nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, if (ret < 0) return; - /* - * If hs clock is unchanged, we're all good - all parameters are - * derived from it atm. - */ - if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate) - return; - phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate); /* Save the new desired phy config */ -- 2.25.1 _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
