--- ./vanilla-3.7/drivers/gpu/drm/radeon/r600.c	2013-01-07 23:02:57.029414308 +0200
+++ ./vanilla-3.7/drivers/gpu/drm/radeon/r600.c	2013-01-11 20:24:15.464141294 +0200
@@ -1382,12 +1382,15 @@ 
 			      u32 disabled_rb_mask)
 {
 	u32 rendering_pipe_num, rb_num_width, req_rb_num;
-	u32 pipe_rb_ratio, pipe_rb_remain;
+	u32 pipe_rb_ratio, pipe_rb_remain, tmp;
 	u32 data = 0, mask = 1 << (max_rb_num - 1);
 	unsigned i, j;
 
 	/* mask out the RBs that don't exist on that asic */
-	disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
+	tmp = disabled_rb_mask | (0xff << max_rb_num) & 0xff;
+	if ((tmp & 0xff) != 0xff)
+		/* only use the formula if it leaves at least one RB available */
+		disabled_rb_mask = tmp;
 
 	rendering_pipe_num = 1 << tiling_pipe_num;
 	req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);