On Fri, Nov 15, 2019 at 04:07:20PM -0500, Lyude Paul wrote: > Noticed this while working on some unrelated CRC stuff. Currently, > userspace has very little support for BPCs higher than 8. While this > doesn't matter for most things, on MST topologies we need to be careful > about ensuring that we do our best to make any given display > configuration fit within the bandwidth restraints of the topology, since > otherwise less people's monitor configurations will work. > > Allowing for BPC settings higher than 8 dramatically increases the > required bandwidth for displays in most configurations, and consequently > makes it a lot less likely that said display configurations will pass > the atomic check. > > In the future we want to fix this correctly by making it so that we > adjust the bpp for each display in a topology to be as high as possible, > while making sure to lower the bpp of each display in the event that we > run out of bandwidth and need to rerun our atomic check. But for now, > follow the behavior that both i915 and amdgpu are sticking to. > > Signed-off-by: Lyude Paul <[email protected]> > Fixes: 232c9eec417a ("drm/nouveau: Use atomic VCPI helpers for MST") > Cc: Ben Skeggs <[email protected]> > Cc: Daniel Vetter <[email protected]> > Cc: David Airlie <[email protected]> > Cc: Jerry Zuo <[email protected]> > Cc: Harry Wentland <[email protected]> > Cc: Juston Li <[email protected]> > Cc: Sam Ravnborg <[email protected]> > Cc: Sean Paul <[email protected]> > Cc: <[email protected]> # v5.1+ > --- > drivers/gpu/drm/nouveau/dispnv50/disp.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Thierry Reding <[email protected]>
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