Acked-by: Slava Abramov <[email protected]> ________________________________ From: amd-gfx <[email protected]> on behalf of Colin King <[email protected]> Sent: Friday, June 28, 2019 10:33:20 AM To: Zhang, Hawking; Deucher, Alexander; Koenig, Christian; Zhou, David(ChunMing); David Airlie; Daniel Vetter; [email protected]; [email protected] Cc: [email protected]; [email protected] Subject: [PATCH] drm/amdgpu: fix a missing break in a switch statement
From: Colin Ian King <[email protected]> Currently for the AMDGPU_IRQ_STATE_DISABLE there is a missing break causing the code to fall through to the AMDGPU_IRQ_STATE_ENABLE case. Fix this by adding in the missing break statement. Addresses-Coverity: ("Missing break in switch") Fixes: a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)") Signed-off-by: Colin Ian King <[email protected]> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 2932ade7dbd0..c165200361b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4608,6 +4608,7 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, 0); WREG32(cp_int_cntl_reg, cp_int_cntl); + break; case AMDGPU_IRQ_STATE_ENABLE: cp_int_cntl = RREG32(cp_int_cntl_reg); cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, -- 2.20.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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