Hi, On Wed, Jun 12, 2019 at 1:51 AM Neil Armstrong <[email protected]> wrote: > > When using an I2S source using a different clock source (usually the I2S > audio HW uses dedicated PLLs, different from the HDMI PHY PLL), fixed > CTS values will cause some frequent audio drop-out and glitches as > reported on Amlogic, Allwinner and Rockchip SoCs setups. > > Setting the CTS in automatic mode will let the HDMI controller generate > automatically the CTS value to match the input audio clock. > > The DesignWare DW-HDMI User Guide explains: > For Automatic CTS generation > Write "0" on the bit field "CTS_manual", Register 0x3205: AUD_CTS3 > > The DesignWare DW-HDMI Databook explains : > If "CTS_manual" bit equals 0b this registers contains "audCTS[19:0]" > generated by the Cycle time counter according to specified timing. > > Cc: Jernej Skrabec <[email protected]> > Cc: Maxime Ripard <[email protected]> > Cc: Jonas Karlman <[email protected]> > Cc: Heiko Stuebner <[email protected]> > Cc: Jerome Brunet <[email protected]> > Signed-off-by: Neil Armstrong <[email protected]> > --- > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 44 +++++++++++++++-------- > 1 file changed, 29 insertions(+), 15 deletions(-)
Tested-by: Douglas Anderson <[email protected]> _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
