Hi Wen,

On Wed, May 15, 2019 at 02:42:08AM +0000, Wen He wrote:
> Disable checking for required pixel clock rate if ARCH_LAYERSCPAE
> is enable.
> 
> Signed-off-by: Alison Wang <[email protected]>
> Signed-off-by: Wen He <[email protected]>
> ---
> change in description:
>       - This check that only supported one pixel clock required clock rate
>       compare with dts node value. but we have supports 4 pixel clock
>       for ls1028a board.

So, your DT says your pixel clock provider is a fixed clock? If you support
more than one rate, you should instead use a real provider for it. How do you
support the 4 pixel clocks?

Also, not sure what the paragraph above is meant to be. Should it be part of
the commit message?

Best regards,
Liviu


>  drivers/gpu/drm/arm/malidp_crtc.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/arm/malidp_crtc.c 
> b/drivers/gpu/drm/arm/malidp_crtc.c
> index 56aad288666e..bb79223d9981 100644
> --- a/drivers/gpu/drm/arm/malidp_crtc.c
> +++ b/drivers/gpu/drm/arm/malidp_crtc.c
> @@ -36,11 +36,13 @@ static enum drm_mode_status malidp_crtc_mode_valid(struct 
> drm_crtc *crtc,
>  
>       if (req_rate) {
>               rate = clk_round_rate(hwdev->pxlclk, req_rate);
> +#ifndef CONFIG_ARCH_LAYERSCAPE
>               if (rate != req_rate) {
>                       DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
>                                        req_rate);
>                       return MODE_NOCLOCK;
>               }
> +#endif
>       }
>  
>       return MODE_OK;
> -- 
> 2.17.1
> 

-- 
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| but they're not |
| giving me the   |
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