On Thu, Dec 20, 2018 at 09:56:57AM -0500, Alex Deucher wrote: > I'm not familiar enough with ARM to know if write combining > is actually an architectural limitation or if it's an issue > with the PCIe IPs used on various platforms, but so far > everyone that has tried to run radeon hardware on > ARM has had to disable it. So let's just make it official.
wc on arm is Really Complicated (tm) afaiui. There's issues with aliasing mappings and stuff, so you need to allocate your wc memory from special pools. So probably best to just disable it until we figure this out. > Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> > --- > include/drm/drm_cache.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h > index bfe1639df02d..691b4c4b0587 100644 > --- a/include/drm/drm_cache.h > +++ b/include/drm/drm_cache.h > @@ -47,6 +47,8 @@ static inline bool drm_arch_can_wc_memory(void) > return false; > #elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3) > return false; > +#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) > + return false; > #else > return true; > #endif > -- > 2.13.6 > > _______________________________________________ > dri-devel mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
