On 04.09.2018 14:10, Laurent Pinchart wrote: > The THC63LVD1024 is restricted to a pixel clock frequency in the range > of 8 to 135 MHz. Implement the bridge .mode_valid() operation > accordingly. > > Signed-off-by: Laurent Pinchart <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]> -- Regards Andrzej _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
