From: Shawn Guo <[email protected]> Some VOU modules do not work well with clock auto-gating. For example, VGA I2C bus will fail to read EDID data from monitor. Let's not enable this feature by default, and leave it to the possible future low-power optimization.
Signed-off-by: Shawn Guo <[email protected]> Reviewed-by: Sean Paul <[email protected]> Acked-by: Daniel Vetter <[email protected]> --- drivers/gpu/drm/zte/zx_vou.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/zte/zx_vou.c b/drivers/gpu/drm/zte/zx_vou.c index cf92d675feaa..2a2d90bd9425 100644 --- a/drivers/gpu/drm/zte/zx_vou.c +++ b/drivers/gpu/drm/zte/zx_vou.c @@ -720,9 +720,6 @@ static void vou_hw_init(struct zx_vou_hw *vou) /* Release reset for all VOU modules */ zx_writel(vou->vouctl + VOU_SOFT_RST, ~0); - /* Enable clock auto-gating for all VOU modules */ - zx_writel(vou->vouctl + VOU_CLK_REQEN, ~0); - /* Enable all VOU module clocks */ zx_writel(vou->vouctl + VOU_CLK_EN, ~0); -- 1.9.1 _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
