Hi Tomi, Thank you for the patch.
On Tuesday 28 Mar 2017 16:07:49 Tomi Valkeinen wrote: > The driver only uses even dividers for hsdiv when pclk >= 100MHz, as odd > dividers can create uneven duty cycle. However, while this holds true > for some dividers like DISPC's LCK and PCK dividers, it is not actually > true for hsdiv. > > hsdiv always produces even duty cycle, so the constraint can be removed. > > Signed-off-by: Tomi Valkeinen <[email protected]> Acked-by: Laurent Pinchart <[email protected]> > --- > drivers/gpu/drm/omapdrm/dss/dpi.c | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c > b/drivers/gpu/drm/omapdrm/dss/dpi.c index e75162d26ac0..e0b0c5c24c55 100644 > --- a/drivers/gpu/drm/omapdrm/dss/dpi.c > +++ b/drivers/gpu/drm/omapdrm/dss/dpi.c > @@ -170,14 +170,6 @@ static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned > long dispc, { > struct dpi_clk_calc_ctx *ctx = data; > > - /* > - * Odd dividers give us uneven duty cycle, causing problem when level > - * shifted. So skip all odd dividers when the pixel clock is on the > - * higher side. > - */ > - if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000) > - return false; > - > ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; > ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; -- Regards, Laurent Pinchart _______________________________________________ dri-devel mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/dri-devel
