It is not necessary to set REG_COC_CTL0, REG_MHL_COC_CTL1 registers.
Signed-off-by: Andrzej Hajda <[email protected]>
---
drivers/gpu/drm/bridge/sil-sii8620.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c
b/drivers/gpu/drm/bridge/sil-sii8620.c
index b2c267d..68cdf63 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -974,12 +974,8 @@ static void sii8620_set_mode(struct sii8620 *ctx, enum
sii8620_mode mode)
);
break;
case CM_MHL3:
- sii8620_write_seq_static(ctx,
- REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
- REG_COC_CTL0, 0x40,
- REG_MHL_COC_CTL1, 0x07
- );
- break;
+ sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
+ return;
case CM_DISCONNECTED:
break;
default:
--
2.7.4
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