The parser and printer is ready on mainline and supports manipulating either TensorIR or low-level TIR. @vinx13 is playing with it right now on GPU codegen.
The TensorIR lowering process is not yet fully on mainline, but let's expect it very soon. @Hzfengsy is almost ready to submit a PR. As @FrozenGene mentioned, it is really challenging when it comes to low-level codegen, and i totally agree with the 4x4/8x8 microkernel approach. --- [Visit Topic](https://discuss.tvm.apache.org/t/do-we-have-any-way-to-process-codegen-with-more-fine-grade-control/9908/6) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/66b59222954ca7f4b7f9cc49eaa17dab7d35738d11dcd68bbf9903be09f730d4).
