Hi @jtuyls / @mak ,
In the TVM-Vitis workflow on ZCU104 platform, what is the memory read/write latency between FPGA and CPU? Is it zero copy? or you do any memory copy and rearrange the memory on the FPGA side? Could you please point us any reference document on this? Thanks and Regards, Raju --- [Visit Topic](https://discuss.tvm.apache.org/t/zero-copy-memory-transfer-between-fpga-and-cpu/9602/1) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/1eec2cbd13bd0cb7a7cd260af14e5b37786d83925784e77a80d7cbd2cb03f256).
