@kwmaeng I've written the sparse_dense kernel for GPUs. It was a little bit of an arduous process, but here are my takeaways:
- Using te only works for some sparse kernels. Sparse kernels are often written as functions over the input tensor. Unfortunately, te requires you to write your kernels as functions over indices in the output tensor. If you can restructure you kernel to be output driven, then you can get around this issue, but other wise your out of luck. - Even If you can write your kernel in te, you may not be able to schedule it. Currently, you cannot apply any scheduling to tensors that are used to control the bounds of a loop. Also, if you have a statement of the form `x[y[i]]` (`x`, `y` are tensors, `i` is an index), you cannot apply any transformations to pull `y[i]` out of `x` (for caching typically). - Given the above two points, you'll probably have to write your kernel in TIR. Currently the best way to do this is `IRBuilder` (tvmscript is still a work in progress and I didn't have as much luck using it). You can see the sparse_dense kernel I wrote here https://github.com/apache/incubator-tvm/blob/main/python/tvm/topi/cuda/sparse.py#L158 for an example of how to use `IRBuilder`. --- [Visit Topic](https://discuss.tvm.apache.org/t/is-sparse-kernel-supported-in-the-tensor-expression-language/8274/3) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/66fb4a323e026f9c60c461c449a88b3d0af1df4089f8ea445c71365c4e6c2116).
