hi @davide-giri,
there's been some work (see below) to optimize TVM-generated code on RISC-V. at `main` today, there isn't anything specific to RISC-V checked-in, but i'm also not aware of anything that would prevent you from running on RISC-V today. could you provide some more clarification which type of RISC-V chip you're interested in (i.e. linux/bare metal, bit width, accelerators)? here are some of the aspects of TVM to consider wrt RISC-V support: - code generation: TVM can emit LLVM IR or C source, so you should be able to compile TVM against a version of LLVM that supports RISC-V code generation (and specify `-mcpu=` and/or `mtriple=` in the target string), or you can compile generated code externally (see the [µTVM compilation flow](https://github.com/apache/incubator-tvm/blob/main/tests/micro/qemu/test_zephyr.py) or using `export_library` directly with the `c` target). - runtime: there are a couple options here: - linux-capable machines can either compile TVM directly and run it with the full Python interpreter (note the compile time may be longer than you'd like). alternatively, you could cross-compile [`apps/bundle_deploy`](https://github.com/apache/incubator-tvm/tree/main/apps/bundle_deploy) and run standalone. - bare metal machines can try the new [Zephyr-based runtime](https://github.com/apache/incubator-tvm/tree/main/tests/micro/qemu/zephyr-runtime). we'll release a VM soon that includes dependencies needed to try this against real hardware. - optimization: as RISC-V is a new platform to TVM, some work needs to be done to make TVM aware of any ISA-specific optimizations. @yrchen has done some [work](https://discuss.tvm.apache.org/t/rfc-enable-tvm-qnn-on-risc-v-with-subword-simd-computation/7967/3) in this area with the RISC-V P extension. - accelerators: i'm not aware of any support for specialized hardware accelerators right now. it should be possible to support these using the [BYOC flow](https://tvm.apache.org/2020/07/15/how-to-bring-your-own-codegen-to-tvm). Andrew --- [Visit Topic](https://discuss.tvm.apache.org/t/can-the-tvm-stack-target-risc-v/8152/3) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/df26a0ea12bae37690b0ebe73547714101cebffd9b86d682545a76f7460baf7a).
