Hi guys,
I'm just beginning to learn tvm, please correct me if anything wrong. we have two products based on FPGAs (Intel Stratix 10 Series), now we are searching for solutions to bring more complex algorithms into FPGAs. 1. the 1st product is a standalone FPGA system, it accept sensors data and do some simple algorithms calculation for check, then send back some data to sensor when detect some signal, and also report event to host app via PCIE/DMA. now we wish to bring more complex algorithms into FPGA for different scenarios, the algorithms may be a DL framework (Like, pytorch) trained model. we propose to implement a new TVM target for IHLS, and a DSL for main logic control, then use generated HLS code and compiled it to RTL code, and build final FPGA binary. does it make sense? for this idea, I'm not very clear on how to generate a proper code for HLS and optimize it in TVM, since HLS have strict input/output requirement and C feature limits. any suggestions? 2. the 2nd product is alse related with FPGA, but it acted as a calculation offload engine like deep learning accelerator. It accept data from host app and return the calculated (only matric multiply) result via PCIE/DMA. currently, the hw design(RTL) was manually developed. now we wish to bring more complex algorithms into it. I found that TVM has a VTA/FPGA backend, I has a more general ISA design, does it work for our solution? or we continue use current design and only replace the calculation module. what's the difference between a general ISA design and a specific algorithm operation design? Thank you very much. --- [Visit Topic](https://discuss.tvm.apache.org/t/need-for-suggestion-for-tvm-with-fpga/8000/1) to respond. You are receiving this because you enabled mailing list mode. To unsubscribe from these emails, [click here](https://discuss.tvm.apache.org/email/unsubscribe/338ea2a462ab525894dddd879f7fcb241ad4c68ad013f9e9593e206fd58b682f).
