On sexta-feira, 21 de setembro de 2012 13.42.13, Tony Van Eerd wrote: > By the way, I assume the intent is to limit the implementation to only using > int/pointer-sized atomics, not double width atomics?
We can use double-width atomics if necessary. But the only architecture for
which I implemented that is x86 32-bit (via cmpxchg8b). And even then, the
assembly is very fragile, since it requires no less than 5 registers and a
memory operand. Very often, gcc bails out by not being able to allocate
registers.
Double-width atomics must be a solution to other problems, not a requirement,
since they don't exist on all platforms. For LL/SC platforms, we need a
different implementation. For Itanium, we must figure out a way of working with
the weird "compare 8 exchange 16" instruction. Finally, for x86-64, we need a
fallback because early 64-bit processors were missing the CMPXCHG16B
instruction.
--
Thiago Macieira - thiago.macieira (AT) intel.com
Software Architect - Intel Open Source Technology Center
Intel Sweden AB - Registration Number: 556189-6027
Knarrarnäsgatan 15, 164 40 Kista, Stockholm, Sweden
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