Hello Emanuel, On Sunday 23 of June 2024 17:15:13 emanuel stiebler wrote: > On 2024-06-21 06:27, Pavel Pisa wrote: > > I want to inform you about the progress of the project. > > > > The CTU local project project links can be found in the > > section CAN/CAN FD Subsystem and Drivers for RTEMS on our page > > > > > > https://canbus.pages.fel.cvut.cz/#cancan-fd-subsystem-and-drivers-for-rte > >ms > > > > The merge request draft for review is available at RTEMS GitLab > > > > https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/49 > > > > and we collect feedback and are preparing enhancements based > > on fedback, i.e. to resolve Gedare noticed problem around > > RTEMS_CAN_CHIP_STOP IOCTL. > > I would actually like to try it. I have some Xilinx MPSoC boards here, > and need some CAN FD (FD is important here). > > But, somehow I can't manage to find the schematics & layouts in KiCAD on > the web? Am I just clicking the wrong buttons? > > I think I found the VHDL sources ...
The VHDL sources of the CTU CAN FD are available from repository https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core the integration into Xilinx Zynq project can be found at https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top There are are more branches, the last CTU CAN FD by Ondrej Ille for our MZ_APO board at branch "mz_apo-2x-xcan-4x-ctu-v25", older/MIT licensed version at branch "mz_apo-2x-xcan-4x-ctu" and build for CAN benchmark board at "can-bench-2x-xcan-4x-ctu". The MZ_APO board schematics and mechanic are available in the source form at https://gitlab.com/pikron/projects/mz_apo/microzed_apo Schematics are in Peter Porazil's PEDA schematic/PCB deign system. But PDF output can be fount for example there https://cmp.felk.cvut.cz/~pisa/apo/mz_apo/ The CAN bench board for CAN latency tester is result of Martin Jerabek's bachelor theses and CTU CAN FD integration has been done as part of his master's theses. Locate them in the list at https://gitlab.fel.cvut.cz/otrees/org/-/wikis/theses-defend Actual files https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top/wikis/uploads/56b4d27d8f81ae390fc98bdce803398f/F3-BP-2016-Jerabek-Martin-Jerabek-thesis-2016.pdf https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf KiCAD design there https://gitlab.fel.cvut.cz/canbus/zynq/canbech-hw PDF export https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top/-/wikis/uploads/93b79611ed12cfb806fcefc6f86973fc/F3-BP-2016-Jerabek-Martin-priloha-CAN-BENCH_Schematics_RevA.pdf But generally, the connection can be really simple, you have CTU CAN FD Vivado component which as APB and CAN Rx and Tx pins and you need to connect CAN/CAN FD transceiver to these, i.e. MCP2562FD or some other. We usually add CAN cross-bar between FPGA CAN Tx/Rx pins and controllers Tx and Rx signals https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top/-/tree/master/system/ip/can_crossbar_2.0 which allows mutual testing and interconnection of multiple controllers to single physical links without need of external jumpers. We have used the design with Zynq 7000 series boards abut even that I have been asked and organized purchase of Xilinx UlraScale systems for the former group, my communication with group after their move to other CTU institute has been disrupted by their actions so we have not checked design with UlraScale. But I expect that there should be no problems. We have tested Altera/Intel SoC and FPGA PCIe cards integration as well as some other FPGAs and technologies and even some other universities report use on some experimental silicon tapeouts. Best wishes, Pavel Pavel Pisa phone: +420 603531357 e-mail: p...@cmp.felk.cvut.cz Department of Control Engineering FEE CVUT Karlovo namesti 13, 121 35, Prague 2 university: http://control.fel.cvut.cz/ personal: http://cmp.felk.cvut.cz/~pisa social: https://social.kernel.org/ppisa projects: https://www.openhub.net/accounts/ppisa CAN related:http://canbus.pages.fel.cvut.cz/ RISC-V education: https://comparch.edu.cvut.cz/ Open Technologies Research Education and Exchange Services https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
