Debugging some qemu interrupts with the uarts on the microblaze platform. I noticed i was getting some transactions failed on the qemu side.
interrupt at pc=802dec88 msr=1a2 0 iflags=100 Transaction failed: vaddr 0x41200024 physaddr 0x0000000041200024 size 4 access type DATA_LOAD Transaction failed: vaddr 0x41200024 physaddr 0x0000000041200024 size 4 access type DATA_STORE Transaction failed: vaddr 0x41200024 physaddr 0x0000000041200024 size 4 access type DATA_STORE This is the interrupt controller. 24 offset is the ILR register 24h ILR Interrupt Level Register (ILR) ``` The Interrupt Level Register (ILR) is a read-write register that contains the ordinal value of the highest priority interrupt prevented from generating a processor IRQ. The ILR provides a method to block lower priority interrupts in order to support nested interrupt handling. When the ILR is 0, no interrupt is allowed to generate IRQ, when the ILR is 1 only INT(0) is allowed to generate IRQ, etc. If all interrupts are allowed to generate IRQ, the ILR should contain all ones. The ILR is shown in Figure 2-10 and described in Table 2-14. Rtems microblaze is most likely writing to this register here. https://github.com/RTEMS/rtems/blob/master/bsps/microblaze/microblaze_fpga/irq/irq.c#L140 Its not totally apparent to me why interrupts are disabled and then re-enable in an interrupt context. Is this needed? I started looking through qemu code, but haven't quite figured out how to patch it to support the irl. >From what i can tell https://github.com/Xilinx/qemu/blob/master/target/microblaze/cpu.c#L153 Interrupt registers actually firing. https://github.com/Xilinx/qemu/blob/master/target/microblaze/helper.c#L180 -- Sincerely, Sam Price _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
