The ARM926EJ-S is an ARMv5T architecture processor and lacks some
features of ARMv6 processors such as the ARM1176JZF-S.
---
bsps/arm/shared/cache/cache-cp15.c | 26 +++++++++++++++++++
.../score/cpu/arm/include/libcpu/arm-cp15.h | 26 ++++++++++++++++---
2 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/bsps/arm/shared/cache/cache-cp15.c
b/bsps/arm/shared/cache/cache-cp15.c
index 1f7132596c..d78ec4feb4 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -200,6 +200,7 @@ static inline void _CPU_cache_disable_instruction(void)
rtems_interrupt_local_enable(level);
}
+#if __ARM_ARCH >= 6
static inline size_t arm_cp15_get_cache_size(
uint32_t level,
uint32_t which
@@ -238,5 +239,30 @@ static inline size_t
_CPU_cache_get_instruction_cache_size(uint32_t level)
{
return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_INSTRUCTION);
}
+#else
+static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
+{
+ uint32_t cache_type;
+
+ if (level > 0) {
+ return 0;
+ }
+
+ cache_type = arm_cp15_get_cache_type();
+ return 1U << (((cache_type >> (12 + 6)) & 0xf) + 9);
+}
+
+static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
+{
+ uint32_t cache_type;
+
+ if (level > 0) {
+ return 0;
+ }
+
+ cache_type = arm_cp15_get_cache_type();
+ return 1U << (((cache_type >> (0 + 6)) & 0xf) + 9);
+}
+#endif
#include "../../shared/cache/cacheimpl.h"
diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
index 333cd7c8a0..c239eaccc8 100644
--- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
+++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
@@ -1309,15 +1309,17 @@ arm_cp15_data_cache_test_and_clean(void)
);
}
-/* In DDI0301H_arm1176jzfs_r0p7_trm
- * 'MCR p15, 0, <Rd>, c7, c14, 0' means
- * Clean and Invalidate Entire Data Cache
- */
ARM_CP15_TEXT_SECTION static inline void
arm_cp15_data_cache_clean_and_invalidate(void)
{
ARM_SWITCH_REGISTERS;
+#if __ARM_ARCH >= 6
+ /*
+ * In DDI0301H_arm1176jzfs_r0p7_trm
+ * 'MCR p15, 0, <Rd>, c7, c14, 0' means
+ * Clean and Invalidate Entire Data Cache
+ */
uint32_t sbz = 0;
__asm__ volatile (
@@ -1328,6 +1330,22 @@ arm_cp15_data_cache_clean_and_invalidate(void)
: [sbz] "r" (sbz)
: "memory"
);
+#else
+ /*
+ * Assume this is an ARM926EJ-S. Use the test, clean, and invalidate DCache
+ * operation.
+ */
+ __asm__ volatile (
+ ARM_SWITCH_TO_ARM
+ "1:\n"
+ "mrc p15, 0, r15, c7, c14, 3\n"
+ "bne 1b\n"
+ ARM_SWITCH_BACK
+ : ARM_SWITCH_OUTPUT
+ :
+ : "memory"
+ );
+#endif
}
ARM_CP15_TEXT_SECTION static inline void
--
2.35.3
_______________________________________________
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
