Hello,
On 26.07.23 22:48, Kinsey Moore wrote:
This adds an option to allow operation of the CPU at its maximum
temperature range of 125F by reducing the CPU clock to 400MHz instead of
the 105F limit imposed by the default 480MHz CPU clock. This tradeoff is
detailed in table 122 in section 7.3.1 of the STM32H743VI datasheet. The
default remains at 480MHz/105F.
I think it is very good to reduce the CPU clock this way. Does your
patch also results in a decrease of operating voltage from VOS0 to VOS1?
In my opinion, the default "480MHz/105F" is not very serious: at that
frequency + temperature, the chip has an expected lifetime of < 2 years.
See:
https://www.st.com/resource/en/application_note/an5337-stm32h7-series-lifetime-estimates-stmicroelectronics.pdf
For our product, we might even reduce the clock further to 300MHZ to be
able to use VOS2 voltage.
All that to say that imho, 1) the default should be 400MHz, and 2) if
there is some configuration variable, maybe it should be based on the
voltage, like "STM23H7_VCORE", with the following values:
- "VOS0": Freq = 480 MHz (the actual default)
- "VOS1": Freq = 400 MHz (your new proposed value)
- "VOS2": Freq = 300 MHz (a very conservative setting)
- "VOS3": Freq = 200 MHz (for very low power usage)
Cedric
---
.../stm/stm32h743i-eval/stm32h7-config-osc.c | 8 ++++++++
spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 2 ++
spec/build/bsps/arm/stm32h7/optenthermal.yml | 18 ++++++++++++++++++
3 files changed, 28 insertions(+)
create mode 100644 spec/build/bsps/arm/stm32h7/optenthermal.yml
diff --git a/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-config-osc.c
b/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-config-osc.c
index df55a49b3c..016f772309 100644
--- a/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-config-osc.c
+++ b/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-config-osc.c
@@ -42,9 +42,17 @@ const RCC_OscInitTypeDef stm32h7_config_oscillator = {
.PLL.PLLState = RCC_PLL_ON,
.PLL.PLLSource = RCC_PLLSOURCE_HSE,
.PLL.PLLM = 5,
+#ifdef STM32H7_OSC_ENABLE_MAX_THERMAL_RANGE
+ .PLL.PLLN = 160,
+#else
.PLL.PLLN = 192,
+#endif
.PLL.PLLP = 2,
+#ifdef STM32H7_OSC_ENABLE_MAX_THERMAL_RANGE
+ .PLL.PLLQ = 2,
+#else
.PLL.PLLQ = 12,
+#endif
.PLL.PLLR = 2,
.PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml
b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml
index 0aaf1f0cc6..2614457bcc 100644
--- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml
+++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml
@@ -13,6 +13,8 @@ install: []
links:
- role: build-dependency
uid: grp
+- role: build-dependency
+ uid: optenthermal
source:
- bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-bspstarthooks.c
- bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-config-clk.c
diff --git a/spec/build/bsps/arm/stm32h7/optenthermal.yml
b/spec/build/bsps/arm/stm32h7/optenthermal.yml
new file mode 100644
index 0000000000..ff79db213d
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optenthermal.yml
@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2023 On-Line Applications Research (OAR)
+default:
+- enabled-by: true
+ value: false
+description: |
+ Allow use of the maximum thermal range the CPU is capable of by reducing the
+ CPU clock to 400MHz
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_OSC_ENABLE_MAX_THERMAL_RANGE
+type: build
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