---
.../dev/cache/arm-data-cache-loop-set-way.h | 11 +++++++++++
bsps/arm/shared/cache/cache-cp15.h | 7 ++++---
bsps/arm/shared/cache/cache-l2c-310.c | 15 +++++++++------
.../shared/cp15/arm-cp15-set-exception-handler.c | 9 +++++++++
bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c | 9 +++++++++
bsps/include/bsp/utility.h | 4 ++--
bsps/shared/dev/irq/arm-gicv2.c | 8 ++++++++
bsps/shared/start/bspfatal-default.c | 9 +++++++++
8 files changed, 61 insertions(+), 11 deletions(-)
diff --git a/bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
b/bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
index 4556fef03d..168b109aa8 100644
--- a/bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
+++ b/bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
@@ -1,3 +1,14 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief This header file provides an assember macro to loop through the data
+ * cache by set and way.
+ */
+
/*
* SPDX-License-Identifier: BSD-2-Clause
*
diff --git a/bsps/arm/shared/cache/cache-cp15.h
b/bsps/arm/shared/cache/cache-cp15.h
index d717a8cf3f..7f1eb87812 100644
--- a/bsps/arm/shared/cache/cache-cp15.h
+++ b/bsps/arm/shared/cache/cache-cp15.h
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
+ * @file
+ *
* @ingroup RTEMSBSPsARMShared
*
- * @brief Level 1 Cache definitions and functions.
- *
- * This file implements handling for the ARM Level 1 cache controller
+ * @brief This header file provides interfaces of the ARM CP15 cache controller
+ * suppport.
*/
/*
diff --git a/bsps/arm/shared/cache/cache-l2c-310.c
b/bsps/arm/shared/cache/cache-l2c-310.c
index 7bfa1a564c..6826043afd 100644
--- a/bsps/arm/shared/cache/cache-l2c-310.c
+++ b/bsps/arm/shared/cache/cache-l2c-310.c
@@ -1,9 +1,10 @@
/**
- * @ingroup L2C-310_cache
+ * @file
*
- * @brief Cache definitions and functions.
+ * @ingroup L2C310CacheSupport
*
- * This file implements handling for the ARM L2C-310 cache controller
+ * @brief This source file contains the implementation of the ARM L2C-310 cache
+ * controller support.
*/
/*
@@ -96,13 +97,15 @@
#define BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK)
/**
- * @defgroup L2C-310_cache Cache Support
+ * @defgroup L2C310CacheSupport L2C-310 Cache Support
+ *
* @ingroup RTEMSBSPsARMShared
- * @brief Cache Functions and Defitions
+ *
+ * @brief This group contains the L2C-310 cache support.
+ *
* @{
*/
-
/**
* @brief L2CC Register Offsets
*/
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
index e97cd2dcbc..39f60e945e 100644
--- a/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
+++ b/bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
@@ -1,5 +1,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief This source file contains the implementation of
+ * arm_cp15_set_exception_handler().
+ */
+
/*
* Copyright (c) 2013 embedded brains GmbH & Co. KG
*
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
index bc8f2a26dd..25ee8103e4 100644
--- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
+++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
@@ -1,5 +1,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief This source file contains the implementation of
+ * arm_cp15_set_translation_table_entries().
+ */
+
/*
* Copyright (C) 2010, 2019 embedded brains GmbH & Co. KG
*
diff --git a/bsps/include/bsp/utility.h b/bsps/include/bsp/utility.h
index d756fed51e..4466a8c9b7 100644
--- a/bsps/include/bsp/utility.h
+++ b/bsps/include/bsp/utility.h
@@ -3,9 +3,9 @@
/**
* @file
*
- * @ingroup bsp_kit
+ * @ingroup RTEMSBSPsShared
*
- * @brief Utility macros.
+ * @brief This header file provides utility macros for BSPs.
*/
/*
diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 3fc66e467d..fcc3d0dfc8 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -1,5 +1,13 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief This source file contains the implementation of ARM GICv2 support.
+ */
+
/*
* Copyright (C) 2013, 2021 embedded brains GmbH & Co. KG
*
diff --git a/bsps/shared/start/bspfatal-default.c
b/bsps/shared/start/bspfatal-default.c
index 9e109c4eb7..557a0960fa 100644
--- a/bsps/shared/start/bspfatal-default.c
+++ b/bsps/shared/start/bspfatal-default.c
@@ -1,5 +1,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief This source file contains the implementation of
+ * bsp_fatal_extension().
+ */
+
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
--
2.35.3
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