On 20/4/2023 12:57 am, Alex White wrote: > This removes the ability to statically configure a second GPIO device. > Instead, any number of GPIO devices can be configured using the device > tree. If a device tree is not used, a single GPIO device can still be > configured statically. > --- > .../microblaze_fpga/gpio/microblaze-gpio.c | 188 ++++++++++++------ > .../include/bsp/microblaze-gpio.h | 91 ++++----- > .../bsps/microblaze/microblaze_fpga/grp.yml | 12 +- > .../microblaze_fpga/optgpio2dualchannel.yml | 16 -- > .../microblaze_fpga/optgpio2enable.yml | 17 -- > .../microblaze_fpga/optgpio2interrupt.yml | 16 -- > .../microblaze_fpga/optgpio2irq.yml | 18 --
Is this for a custom FPGA image? Are the IP pieces being used standard Xilinx IP? Could those IP pieces be used on a Zynq or Versal? If so how would that happen? We have other Xilinx IP in RTEMS without being specific to a BSP or using YAML configuration options. The AXI I2C master is an example. Chris _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
