To ensure data consistency, the cache much be flushed before disabling
the MMU. When the MMU is disabled, all accesses are treated as
non-cachced and thus will bypass the cache.
---
bsps/aarch64/include/bsp/aarch64-mmu.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
b/bsps/aarch64/include/bsp/aarch64-mmu.h
index ebc224b9e1..2101ef4ae0 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -420,7 +420,13 @@ aarch64_mmu_disable( void )
{
uint64_t sctlr;
- /* Enable MMU and cache */
+ /*
+ * Flush data cache before disabling the MMU. While the MMU is disabled, all
+ * accesses are treated as uncached device memory.
+ */
+ rtems_cache_flush_entire_data();
+
+ /* Disable MMU */
sctlr = _AArch64_Read_sctlr_el1();
sctlr &= ~(AARCH64_SCTLR_EL1_M);
_AArch64_Write_sctlr_el1( sctlr );
--
2.30.2
_______________________________________________
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
