On Tue, Nov 1, 2022 at 3:59 PM Chris Johns <chr...@rtems.org> wrote: > On 2/11/2022 5:38 am, Kinsey Moore wrote:> +#ifdef > BSP_XILINX_ZYNQMP_MGMT_UART_BASE > > +/** > > + * @brief Zynq UltraScale+ MPSoC specific set up of a management > console. > > + * > > + * The ZynqMP SoC's programmable logic can provide a serial interface > for system > > + * management which may need special initialization. Provide in the > application > > + * to override the defaults in the BSP. > > + */ > > I am not comfortable with PL implementation dependences for specific > hardware > being added to the generic BSP code. The Zynq, ZymqMP and Versal have so > far > only referenced the hard IP. > > Is the PL project and implementation for the PL logic openly available? > > Unfortunately, not as far as I'm aware. The management interface is guaranteed to exist as a 16550 UART on all variants of the system and, from the RTEMS perspective, the PL is a locked/hard part of the system.
> The hardware requires I request a data sheet from the manufacturer and that > makes keeping this code in our open repo difficult. > I understand. The unfortunate part of this is that RTEMS isn't usable on this platform beyond a couple of seconds without pushing off the system watchdog via the 16550 UART. I have automated the watchdog parameter manipulation externally for testing purposes, but a system running outside that harness would encounter problems with many tests in the testsuite. Kinsey
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