The BSD SD subsystem enforces a 50MHz clock cap for devices which don't
report their own maximum clock speed. This setting is unnecessary for
the Zynq 7000 version of this IP and restricts the Zynq Ultrascale+
MPSoC version of this IP without need since it reports its maximum speed
as 200MHz.
---
rtemsbsd/sys/dev/sdhci/arasan_sdhci.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/rtemsbsd/sys/dev/sdhci/arasan_sdhci.c
b/rtemsbsd/sys/dev/sdhci/arasan_sdhci.c
index 43231113..bac6b148 100644
--- a/rtemsbsd/sys/dev/sdhci/arasan_sdhci.c
+++ b/rtemsbsd/sys/dev/sdhci/arasan_sdhci.c
@@ -284,8 +284,6 @@ arasan_sdhci_attach(device_t dev)
*/
sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
- sc->slot.max_clk = 50000000;
-
sdhci_init_slot(dev, &sc->slot, 0);
sc->slot_init_done = true;
--
2.30.2
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