The Versal's DDRMC0 supports two separate regions. Region 0 is from 0 up to 2G where the Versal's hard IP regions start. DDR memory above the 2G mark is moved to region 1 and its base address is in the A64 address space.
The patch will place all memory up to 2G in region 0 and if more is present it is located in region 1. An MMU entry for the region 1 memory is provided and the memory is added to the heap. Chris _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
