On 20/7/2022 2:58 am, Kinsey Moore wrote: > This alters the AArch64 page table generation and mapping code and MMU > configuration to use page table level 0 in addition to levels 1, 2, and > 3. This allows the mapping of up to 48 bits of memory space and is the > maximum that can be mapped without relying on additional processor > extensions. Mappings are restricted based on the number of physical > address bits that the CPU supports.
OK to push. I have tested this with 8G of memory mapped to the Versal's DDRCM0_region0_mem and DDRCM0_region1_mem address spaces. Thanks Chris _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
