---
bsps/arm/stm32h7/console/console-usart1-cfg.c | 8 +--
bsps/arm/stm32h7/start/bspstarthooks.c | 2 +-
bsps/arm/stm32h7/start/stm32h7-config-clk.c | 4 ++
bsps/arm/stm32h7/start/stm32h7-config-fls.c | 8 ++-
bsps/arm/stm32h7/start/stm32h7-config-osc.c | 17 +++++++
bsps/arm/stm32h7/start/stm32h7-config-per.c | 17 +++++++
bsps/arm/stm32h7/start/stm32h7-hal-eth.c | 4 ++
bsps/arm/stm32h7/start/stm32h7-hal.c | 20 ++++++++
bsps/arm/stm32h7/start/system_stm32h7xx.c | 51 ++++++++++++++++---
.../bsps/arm/stm32h7/bspstm32h7b3i-dk.yml | 17 +++++++
spec/build/bsps/arm/stm32h7/grp.yml | 8 +++
spec/build/bsps/arm/stm32h7/optenuart5.yml | 5 +-
spec/build/bsps/arm/stm32h7/optenuart7.yml | 5 +-
spec/build/bsps/arm/stm32h7/optenuart8.yml | 5 +-
spec/build/bsps/arm/stm32h7/optenuart9.yml | 5 +-
spec/build/bsps/arm/stm32h7/optenusart10.yml | 5 +-
spec/build/bsps/arm/stm32h7/optenusart3.yml | 5 +-
spec/build/bsps/arm/stm32h7/optenusart6.yml | 5 +-
spec/build/bsps/arm/stm32h7/opthse.yml | 3 ++
.../build/bsps/arm/stm32h7/optmemsdram1sz.yml | 5 +-
spec/build/bsps/arm/stm32h7/optmemsram1sz.yml | 5 +-
spec/build/bsps/arm/stm32h7/optmemsram2sz.yml | 5 +-
spec/build/bsps/arm/stm32h7/optmemsram3sz.yml | 5 +-
spec/build/bsps/arm/stm32h7/optmemsram4sz.yml | 5 +-
.../bsps/arm/stm32h7/optmemsramaxisz.yml | 5 +-
spec/build/bsps/arm/stm32h7/optpwrsupply.yml | 19 +++++++
.../arm/stm32h7/optusart1alternatefunc.yml | 19 +++++++
.../bsps/arm/stm32h7/optusart1gpiopins.yml | 19 +++++++
.../bsps/arm/stm32h7/optusart1gpioregs.yml | 19 +++++++
spec/build/bsps/arm/stm32h7/optvariant.yml | 5 +-
30 files changed, 279 insertions(+), 26 deletions(-)
create mode 100644 spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optpwrsupply.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optusart1alternatefunc.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml
create mode 100644 spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
diff --git a/bsps/arm/stm32h7/console/console-usart1-cfg.c
b/bsps/arm/stm32h7/console/console-usart1-cfg.c
index 47c13b2f54..d64d91ab30 100644
--- a/bsps/arm/stm32h7/console/console-usart1-cfg.c
+++ b/bsps/arm/stm32h7/console/console-usart1-cfg.c
@@ -31,15 +31,17 @@
#include <stm32h7/hal.h>
+#include <bspopts.h>
+
const stm32h7_uart_config stm32h7_usart1_config = {
.gpio = {
- .regs = GPIOB,
+ .regs = STM32H7_USART1_GPIO_REGS,
.config = {
- .Pin = GPIO_PIN_14 | GPIO_PIN_15,
+ .Pin = STM32H7_USART1_GPIO_PINS,
.Mode = GPIO_MODE_AF_PP,
.Pull = GPIO_NOPULL,
.Speed = GPIO_SPEED_FREQ_LOW,
- .Alternate = GPIO_AF4_USART1
+ .Alternate = STM32H7_USART1_ALT_FUNC
}
},
.irq = USART1_IRQn,
diff --git a/bsps/arm/stm32h7/start/bspstarthooks.c
b/bsps/arm/stm32h7/start/bspstarthooks.c
index dcd4b0bef2..ef26af5eba 100644
--- a/bsps/arm/stm32h7/start/bspstarthooks.c
+++ b/bsps/arm/stm32h7/start/bspstarthooks.c
@@ -43,7 +43,7 @@ void HAL_MspInit(void)
static void init_power(void)
{
- HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+ HAL_PWREx_ConfigSupply(STM32H7_PWR_SUPPLY);
__HAL_PWR_VOLTAGESCALING_CONFIG(stm32h7_config_pwr_regulator_voltagescaling);
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c
b/bsps/arm/stm32h7/start/stm32h7-config-clk.c
index 3e7c930201..4c25241b99 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config-clk.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-clk.c
@@ -37,7 +37,11 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = {
| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
.SYSCLKDivider = RCC_SYSCLK_DIV1,
+#ifdef STM32H7B3xxQ
+ .AHBCLKDivider = RCC_HCLK_DIV1,
+#else
.AHBCLKDivider = RCC_HCLK_DIV2,
+#endif
.APB3CLKDivider = RCC_APB3_DIV2,
.APB1CLKDivider = RCC_APB1_DIV2,
.APB2CLKDivider = RCC_APB2_DIV2,
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-fls.c
b/bsps/arm/stm32h7/start/stm32h7-config-fls.c
index f2d10d2410..65a25df3f0 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config-fls.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-fls.c
@@ -31,4 +31,10 @@
#include <stm32h7/hal.h>
-const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4;
+const uint32_t stm32h7_config_flash_latency
+#ifdef STM32H7B3xxQ
+ = FLASH_LATENCY_6;
+#else
+ = FLASH_LATENCY_4;
+#endif
+
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-osc.c
b/bsps/arm/stm32h7/start/stm32h7-config-osc.c
index b639c7ca36..f790201e5a 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config-osc.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-osc.c
@@ -32,6 +32,22 @@
#include <stm32h7/hal.h>
const RCC_OscInitTypeDef stm32h7_config_oscillator = {
+#ifdef STM32H7B3xxQ
+ .OscillatorType = RCC_OSCILLATORTYPE_HSE,
+ .HSEState = RCC_HSE_ON,
+ .HSIState = RCC_HSI_OFF,
+ .CSIState = RCC_CSI_OFF,
+ .PLL.PLLState = RCC_PLL_ON,
+ .PLL.PLLSource = RCC_PLLSOURCE_HSE,
+ .PLL.PLLM = 12,
+ .PLL.PLLN = 280,
+ .PLL.PLLFRACN = 0,
+ .PLL.PLLP = 2,
+ .PLL.PLLR = 2,
+ .PLL.PLLQ = 2,
+ .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
+ .PLL.PLLRGE = RCC_PLL1VCIRANGE_1,
+#else
.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48,
.HSEState = RCC_HSE_ON,
@@ -49,4 +65,5 @@ const RCC_OscInitTypeDef stm32h7_config_oscillator = {
.PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
.PLL.PLLFRACN = 0
+#endif
};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-per.c
b/bsps/arm/stm32h7/start/stm32h7-config-per.c
index 79aa1494dd..ce6370d3d0 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config-per.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-per.c
@@ -32,6 +32,22 @@
#include <stm32h7/hal.h>
const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
+#ifdef STM32H7B3xxQ
+ /* for stm32h7b3i-dk BSP we provide only minimalistic peripheral
+ configuration just to make available U(S)ARTs working */
+ .PeriphClockSelection = RCC_PERIPHCLK_USART3
+ | RCC_PERIPHCLK_USART1,
+ .PLL2.PLL2M = 24,
+ .PLL2.PLL2N = 200,
+ .PLL2.PLL2P = 0,
+ .PLL2.PLL2Q = 2,
+ .PLL2.PLL2R = 0,
+ .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2,
+ .PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM,
+ .PLL2.PLL2FRACN = 0,
+ .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
+ .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
+#else
.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
| RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG,
@@ -59,4 +75,5 @@ const RCC_PeriphCLKInitTypeDef
stm32h7_config_peripheral_clocks = {
.UsbClockSelection = RCC_USBCLKSOURCE_PLL3,
.RTCClockSelection = RCC_RTCCLKSOURCE_LSE,
.RngClockSelection = RCC_RNGCLKSOURCE_HSI48
+#endif
};
diff --git a/bsps/arm/stm32h7/start/stm32h7-hal-eth.c
b/bsps/arm/stm32h7/start/stm32h7-hal-eth.c
index b9dac6d7f9..5fc75f0147 100644
--- a/bsps/arm/stm32h7/start/stm32h7-hal-eth.c
+++ b/bsps/arm/stm32h7/start/stm32h7-hal-eth.c
@@ -33,6 +33,8 @@
#include <bspopts.h>
+#ifndef STM32H7B3xxQ
+
static const stm32h7_gpio_config gpiog = {
.regs = GPIOG,
.config = {
@@ -94,3 +96,5 @@ HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
stm32h7_gpio_init(&gpiob);
#endif
}
+
+#endif
diff --git a/bsps/arm/stm32h7/start/stm32h7-hal.c
b/bsps/arm/stm32h7/start/stm32h7-hal.c
index d042a5b8c9..ecd8e4218a 100644
--- a/bsps/arm/stm32h7/start/stm32h7-hal.c
+++ b/bsps/arm/stm32h7/start/stm32h7-hal.c
@@ -132,13 +132,23 @@ static const stm32h7_clk_info stm32h7_clk[] = {
[STM32H7_MODULE_USART10] = { NULL, 0 },
#endif
[STM32H7_MODULE_RNG] = { &RCC->AHB2ENR, RCC_AHB2ENR_RNGEN },
+#ifdef RCC_AHB1ENR_ETH1MACEN
[STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN },
+#endif
+#ifdef RCC_AHB1ENR_ETH1TXEN
[STM32H7_MODULE_ETH1TX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN },
+#endif
+#ifdef RCC_AHB1ENR_ETH1RXEN
[STM32H7_MODULE_ETH1RX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN },
+#endif
[STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN },
[STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1ENR,
RCC_AHB1ENR_USB1OTGHSULPIEN },
+#ifdef RCC_AHB1ENR_USB20TGHSEN
[STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN },
+#endif
+#ifdef RCC_AHB1ENR_USB20TGHSULPIEN
[STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1ENR,
RCC_AHB1ENR_USB2OTGHSULPIEN },
+#endif
[STM32H7_MODULE_SDMMC1] = { &RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN },
[STM32H7_MODULE_SDMMC2] = { &RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN },
};
@@ -205,13 +215,23 @@ static const stm32h7_clk_info stm32h7_clk_low_power[] = {
[STM32H7_MODULE_USART10] = { NULL, 0 },
#endif
[STM32H7_MODULE_RNG] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN },
+#ifdef RCC_AHB1LPENR_ETH1MACLPEN
[STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN },
+#endif
+#ifdef RCC_AHB1LPENR_ETH1TXLPEN
[STM32H7_MODULE_ETH1TX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN },
+#endif
+#ifdef RCC_AHB1LPENR_ETH1RXLPEN
[STM32H7_MODULE_ETH1RX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN },
+#endif
[STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSLPEN },
[STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1LPENR,
RCC_AHB1LPENR_USB1OTGHSULPILPEN },
+#ifdef RCC_AHB1LPENR_USB2OTGHSLPEN
[STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSLPEN },
+#endif
+#ifdef RCC_AHB1LPENR_USB2OTGHSULPILPEN
[STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1LPENR,
RCC_AHB1LPENR_USB2OTGHSULPILPEN },
+#endif
[STM32H7_MODULE_SDMMC1] = { &RCC->AHB3LPENR, RCC_AHB3LPENR_SDMMC1LPEN },
[STM32H7_MODULE_SDMMC2] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN },
};
diff --git a/bsps/arm/stm32h7/start/system_stm32h7xx.c
b/bsps/arm/stm32h7/start/system_stm32h7xx.c
index 092d853720..1f0fd04dab 100644
--- a/bsps/arm/stm32h7/start/system_stm32h7xx.c
+++ b/bsps/arm/stm32h7/start/system_stm32h7xx.c
@@ -51,7 +51,11 @@
#include <bsp/linker-symbols.h>
#endif /* __rtems__ */
#if !defined (HSE_VALUE)
+#ifdef STM32H7B3xxQ
+#define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External
oscillator in Hz */
+#else
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External
oscillator in Hz */
+#endif
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
@@ -147,9 +151,9 @@
*/
void SystemInit (void)
{
-#if defined (DATA_IN_D2_SRAM)
+#if defined (DATA_IN_D2_SRAM) || defined (DATA_IN_CD_AHB_SRAM)
__IO uint32_t tmpreg;
-#endif /* DATA_IN_D2_SRAM */
+#endif /* DATA_IN_D2_SRAM || DATA_IN_CD_AHB_SRAM */
/* FPU settings
------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
@@ -184,6 +188,26 @@ void SystemInit (void)
/* Reset SRDCFGR register */
RCC->SRDCFGR = 0x00000000;
#endif
+#ifdef STM32H7B3xxQ
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x02020200;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x01FF0000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x01010280;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x01010280;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x01010280;
+#else
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x00000000;
@@ -202,7 +226,7 @@ void SystemInit (void)
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x00000000;
-
+#endif
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
@@ -222,25 +246,34 @@ void SystemInit (void)
}
#endif
-#ifndef __rtems__
#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM
clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN |
RCC_AHB2ENR_D2SRAM3EN);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#elif DATA_IN_CD_AHB_SRAM
+ /* in case of initialized data in CD AHB SRAM, enable the CD AHB SRAM clock
*/
+ RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#else
RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
#endif /* RCC_AHB2ENR_D2SRAM3EN */
-
+#endif /* DATA_IN_D2_SRAM */
+#ifndef __rtems__
tmpreg = RCC->AHB2ENR;
(void) tmpreg;
-#endif /* DATA_IN_D2_SRAM */
#else /* __rtems__ */
- RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN |
RCC_AHB2ENR_D2SRAM3EN);
RCC->AHB2ENR;
#endif /* __rtems__ */
+#ifdef STM32H7B3xxQ
+/*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use
of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+#endif
#ifndef __rtems__
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4
------------------*/
@@ -254,7 +287,11 @@ void SystemInit (void)
/* Configure the Vector Table location add offset address for cortex-M7
------------------*/
#ifdef VECT_TAB_SRAM
+#ifdef STM32H7B3xxQ
+ SCB->VTOR = CD_AXISRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation
in Internal CD AXI-RAM */
+#else
SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation
in Internal AXI-RAM */
+#endif
#else
SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation
in Internal FLASH */
#endif
diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml
b/spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml
new file mode 100644
index 0000000000..b33bf99826
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/bspstm32h7b3i-dk.yml
@@ -0,0 +1,17 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: arm
+bsp: stm32h7b3i-dk
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2022 Karel Gardas <karel@functional.vision>
+cppflags: []
+enabled-by: true
+family: stm32h7
+includes: []
+install: []
+links:
+- role: build-dependency
+ uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/grp.yml
b/spec/build/bsps/arm/stm32h7/grp.yml
index 5e26a3e072..e3b44d9593 100644
--- a/spec/build/bsps/arm/stm32h7/grp.yml
+++ b/spec/build/bsps/arm/stm32h7/grp.yml
@@ -79,6 +79,14 @@ links:
uid: optmemsrambackupsz
- role: build-dependency
uid: optprintkinstance
+- role: build-dependency
+ uid: optpwrsupply
+- role: build-dependency
+ uid: optusart1gpiopins
+- role: build-dependency
+ uid: optusart1gpioregs
+- role: build-dependency
+ uid: optusart1alternatefunc
- role: build-dependency
uid: optusart3gpiopins
- role: build-dependency
diff --git a/spec/build/bsps/arm/stm32h7/optenuart5.yml
b/spec/build/bsps/arm/stm32h7/optenuart5.yml
index f124d72113..413f9447b8 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart5.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart5.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart7.yml
b/spec/build/bsps/arm/stm32h7/optenuart7.yml
index 7310cef713..c9884fcb46 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart7.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart7.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart8.yml
b/spec/build/bsps/arm/stm32h7/optenuart8.yml
index f0407f6510..593f736970 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart8.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart8.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenuart9.yml
b/spec/build/bsps/arm/stm32h7/optenuart9.yml
index 1a3ef49459..596aae59ef 100644
--- a/spec/build/bsps/arm/stm32h7/optenuart9.yml
+++ b/spec/build/bsps/arm/stm32h7/optenuart9.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart10.yml
b/spec/build/bsps/arm/stm32h7/optenusart10.yml
index 659d1a96b6..d5c5a1906e 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart10.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart10.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart3.yml
b/spec/build/bsps/arm/stm32h7/optenusart3.yml
index 09e673ff7f..f74ea31fa3 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart3.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart3.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optenusart6.yml
b/spec/build/bsps/arm/stm32h7/optenusart6.yml
index e6524fd40d..51791b56cd 100644
--- a/spec/build/bsps/arm/stm32h7/optenusart6.yml
+++ b/spec/build/bsps/arm/stm32h7/optenusart6.yml
@@ -3,7 +3,10 @@ actions:
- define-condition: null
build-type: option
default: true
-default-by-variant: []
+default-by-variant:
+- value: false
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/opthse.yml
b/spec/build/bsps/arm/stm32h7/opthse.yml
index 51366932e1..e5feef1114 100644
--- a/spec/build/bsps/arm/stm32h7/opthse.yml
+++ b/spec/build/bsps/arm/stm32h7/opthse.yml
@@ -9,6 +9,9 @@ default-by-variant:
- value: 8000000
variants:
- arm/nucleo-h743zi
+- value: 24000000
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
index 11228ddb92..b748d7d3f7 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsdram1sz.yml
@@ -3,7 +3,10 @@ actions:
- env-assign: null
build-type: option
default: 33554432
-default-by-variant: []
+default-by-variant:
+- value: 0
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml
index 01e9dbe1cc..8e071f0939 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsram1sz.yml
@@ -3,7 +3,10 @@ actions:
- env-assign: null
build-type: option
default: 0x20000
-default-by-variant: []
+default-by-variant:
+- value: 0x10000
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml
index 2a4890730a..782d7ba58c 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsram2sz.yml
@@ -3,7 +3,10 @@ actions:
- env-assign: null
build-type: option
default: 0x20000
-default-by-variant: []
+default-by-variant:
+- value: 0x10000
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml
index eca335fd81..a4cd8c4eda 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsram3sz.yml
@@ -3,7 +3,10 @@ actions:
- env-assign: null
build-type: option
default: 0x8000
-default-by-variant: []
+default-by-variant:
+- value: 0x0
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml
b/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml
index cda2e722a4..9749bdfc6a 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsram4sz.yml
@@ -3,7 +3,10 @@ actions:
- env-assign: null
build-type: option
default: 0x10000
-default-by-variant: []
+default-by-variant:
+- value: 0x8000
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml
b/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml
index 9cb05540b7..89e116c1de 100644
--- a/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml
+++ b/spec/build/bsps/arm/stm32h7/optmemsramaxisz.yml
@@ -3,7 +3,10 @@ actions:
- env-assign: null
build-type: option
default: 0x80000
-default-by-variant: []
+default-by-variant:
+- value: 0xA0000
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{:#010x}'
links: []
diff --git a/spec/build/bsps/arm/stm32h7/optpwrsupply.yml
b/spec/build/bsps/arm/stm32h7/optpwrsupply.yml
new file mode 100644
index 0000000000..d7eeb63906
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optpwrsupply.yml
@@ -0,0 +1,19 @@
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+default: PWR_LDO_SUPPLY
+default-by-variant:
+- value: PWR_DIRECT_SMPS_SUPPLY
+ variants:
+ - arm/stm32h7b3i-dk
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_PWR_SUPPLY
+description: |
+ Board power supply mechanism configuration. WARNING: wrong configuration
here may result in your board being unaccessible using ST-Link interface!
Please consult board datasheet for more information about various power supply
options and about how to fix possible misconfiguration.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2022 Karel Gardas <karel@functional.vision>
diff --git a/spec/build/bsps/arm/stm32h7/optusart1alternatefunc.yml
b/spec/build/bsps/arm/stm32h7/optusart1alternatefunc.yml
new file mode 100644
index 0000000000..049ed6a3ac
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optusart1alternatefunc.yml
@@ -0,0 +1,19 @@
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+default: GPIO_AF4_USART1
+default-by-variant:
+- value: GPIO_AF7_USART1
+ variants:
+ - arm/stm32h7b3i-dk
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_USART1_ALT_FUNC
+description: |
+ Alternate function mapping for the USART1 pin configuration.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2022 Karel Gardas <karel@functional.vision>
diff --git a/spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml
b/spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml
new file mode 100644
index 0000000000..1580ded243
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optusart1gpiopins.yml
@@ -0,0 +1,19 @@
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+default: ( GPIO_PIN_14 | GPIO_PIN_15 )
+default-by-variant:
+- value: ( GPIO_PIN_9 | GPIO_PIN_10 )
+ variants:
+ - arm/stm32h7b3i-dk
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_USART1_GPIO_PINS
+description: |
+ GPIO pins used for the USART1 pin configuration.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021-22 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
b/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
new file mode 100644
index 0000000000..46d10616bb
--- /dev/null
+++ b/spec/build/bsps/arm/stm32h7/optusart1gpioregs.yml
@@ -0,0 +1,19 @@
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+default: GPIOD
+default-by-variant:
+- value: GPIOA
+ variants:
+ - arm/stm32h7b3i-dk
+enabled-by: true
+format: '{}'
+links: []
+name: STM32H7_USART1_GPIO_REGS
+description: |
+ GPIO registers used for the USART1 pin configuration.
+type: build
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+copyrights:
+- Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
diff --git a/spec/build/bsps/arm/stm32h7/optvariant.yml
b/spec/build/bsps/arm/stm32h7/optvariant.yml
index 586fa2052b..5d77ece120 100644
--- a/spec/build/bsps/arm/stm32h7/optvariant.yml
+++ b/spec/build/bsps/arm/stm32h7/optvariant.yml
@@ -13,7 +13,10 @@ actions:
conf.define_cond(value, True)
build-type: option
default: STM32H743xx
-default-by-variant: []
+default-by-variant:
+- value: STM32H7B3xxQ
+ variants:
+ - arm/stm32h7b3i-dk
enabled-by: true
format: '{}'
links: []
--
2.25.1
_______________________________________________
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
