On Fri, Dec 10, 2021 at 10:19 AM Sebastian Huber <sebastian.hu...@embedded-brains.de> wrote: > > On 10/12/2021 16:49, Kinsey Moore wrote: > > The AArch64 cache implementation does not define > > rtems_cache_disable_data(), but declares that it does via > > CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA. The existing implementation of > > _CPU_cache_disable_data() is sufficient to enable this functionality > > without the erroneous cache feature flag. > > > > Closes #4569 > > Thanks, please check it in. > > At least for ARMv7 we have an assembler implementation for this function: > > bsps/arm/shared/cache/cache-v7ar-disable-data.S > Basically the same code should work for aarch64, replacing the access with SCTLR_EL3 mrs x0, SCTLR_EL1 bic x0, x0, #0x4 msr SCTLR_EL1, x0 isb
> -- > embedded brains GmbH > Herr Sebastian HUBER > Dornierstr. 4 > 82178 Puchheim > Germany > email: sebastian.hu...@embedded-brains.de > phone: +49-89-18 94 741 - 16 > fax: +49-89-18 94 741 - 08 > > Registergericht: Amtsgericht München > Registernummer: HRB 157899 > Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler > Unsere Datenschutzerklärung finden Sie hier: > https://embedded-brains.de/datenschutzerklaerung/ > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
