On Sat, Oct 2, 2021, 3:59 AM Hesham Almatary <hesham.almat...@cl.cam.ac.uk> wrote:
> On Sat, 2 Oct 2021 at 02:44, Chris Johns <chr...@rtems.org> wrote: > > > > On 1/10/21 3:43 pm, Alex White wrote: > > > bsps/microblaze/include/common/xil_types.h | 197 +++ > > > bsps/microblaze/include/dev/serial/uartlite.h | 62 + > > > .../include/dev/serial/uartlite_l.h | 323 +++++ > > > bsps/microblaze/shared/dev/serial/uartlite.c | 145 ++ > > > .../microblaze/shared/dev/serial/uartlite_l.c | 99 ++ > > > > Are these Xilinx files shared in the their SDK? > > > Yes > > https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartlite/src > > > Should we start here and then move to a generic location if used on > another > > architecture? > > > I agree. It's the same case for uart16550. uartlite IP core can be > used for other soft-core like RISC-V on Xilinx-based FPGAs > > > > .../microblaze_fpga/startup/sim-crtinit.S | 46 +- > > > > FPGA or simulator? The naming seems to contradict it self. > That's likely me building on Joel's first port on GDB, then using the > same file name and modifying it to run on FPGA. Should be renamed to > start.S or something. > I took that file from somewhere else with that name. Probably from libgloss. Alex and I can look at naming it something else though. --joel > > > > > Chris > > _______________________________________________ > > devel mailing list > > devel@rtems.org > > http://lists.rtems.org/mailman/listinfo/devel > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel > _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
