On Wed, Jun 23, 2021 at 7:55 PM Kinsey Moore <kinsey.mo...@oarcorp.com> wrote: > > Looks good. It's odd that we can't step down from EL3->EL2S->EL1S > and have the timer work on the versal. It'd be nice if we could just flip > the security bit one way or the other on the way down and share the > cascade from EL3 to EL1 without skipping parts of it. This might be > something to look into further in the future. > Thanks. I agree. The problem seems to be that HCR_EL2 is ignored if (SCR_EL3.EEL2 = 0 && SCR_EL3.NS = 0). So, you either need to set the non-secure mode, or you need to set EL2 security mode, which then traps into EL2 on some accesses in Secure EL1. I wasn't able to figure out if it's possible for EL2 to avoid those traps.
When I did enable SCR_EL3.EEL2 and tried to do the EL2 -> EL1S drop, the eret comes back to _el2_start instead of _el1_start. I couldn't figure that one out. https://developer.arm.com/documentation/ddi0595/2020-12/AArch64-Registers/SCR-EL3--Secure-Configuration-Register?lang=en Gedare > Kinsey > > -----Original Message----- > From: devel <devel-boun...@rtems.org> On Behalf Of Gedare Bloom > Sent: Tuesday, June 22, 2021 23:30 > To: devel@rtems.org > Subject: [PATCH 0/6] Add aarch64/xilinx-versal > > This patch series adds support for the Xilinx Versal ACAP > targeting the qemu emulated support (xlnx-versal-virt) and > with a config for vck190. The hardware support on vck190 is > still work-in-progress, and the ilp32 has not been tested. > > The patch set includes non-functional changes to make the > icspicfgr0/1 an array for better indexing, to add the > physical secure timer, and a mnemonic to access the group 1 > interrupt enable at EL3. These non-functional changes wound > up being unnecessary, but were left in case they are useful > to someone in the future. The virtual and physical secure timers > do not work with the xilinx_versal_lp64_qemu BSP. Only the > physical non-secure timer works, and only in EL1 security mode. > > The xlnx-versal-virt direct boots on qemu in EL3. The current > approach steps down directly to EL1 in Secure Mode. If EL3 is > instead stepped down to EL2 and then to EL1 non-secure, the > timer IRQ dispatching does not work properly for some reason. > So now we have support in place to run in EL1 Secure mode > or in EL1 Non-Secure mode, controlled by a configuration option. > The a53 and a72 BSPs can only work in the EL1 Non-Secure mode, > while the xilinx_zynq_lp64_qemu seems to be able to work with > both EL1 Secure and Non-Secure modes. The selection is made by > a new config option, AARCH_IS_NON_SECURE. > > Tester Results for xilinx_versal_lp64_qemu: > > Passed: 549 > Failed: 1 > User Input: 5 > Expected Fail: 0 > Indeterminate: 0 > Benchmark: 3 > Timeout: 0 > Test too long: 0 > Invalid: 0 > Wrong Version: 0 > Wrong Build: 0 > Wrong Tools: 0 > ------------------ > Total: 558 > Failures: > spcpucounter01.exe > User Input: > top.exe > fileio.exe > capture.exe > monitor.exe > termios.exe > Benchmark: > dhrystone.exe > whetstone.exe > linpack.exe > > The failure in spcpucounter01.exe appears to be related to the > ongoing problem with qemu random failures. Manual testing can > pass or fail. > > No regressions noted in a53, a72, or zynqmp qemu testing. > > Gedare Bloom (5): > aarch64/xilinx-versal: new BSPs for qemu and vck190 > bsps/dev/irq: make icspicfgr an indexable array > bsps/aarch64: add mnemonic for ICC_IGRPEN1_EL3 > bsps/aarch64: add physical secure timer > bsps/aarch64: add non-secure mode and versal support > > Kinsey Moore (1): > aarch64: add support to drop EL3 to EL2 > > .../shared/clock/arm-generic-timer-aarch64.c | 8 + > bsps/aarch64/shared/start/start.S | 38 ++- > bsps/aarch64/xilinx-versal/console/console.c | 134 ++++++++++ > .../dev/serial/versal-uart-polled.c | 228 ++++++++++++++++++ > bsps/aarch64/xilinx-versal/include/bsp.h | 81 +++++++ > bsps/aarch64/xilinx-versal/include/bsp/irq.h | 72 ++++++ > .../include/dev/serial/versal-uart-regs.h | 141 +++++++++++ > .../include/dev/serial/versal-uart.h | 90 +++++++ > bsps/aarch64/xilinx-versal/include/tm27.h | 45 ++++ > bsps/aarch64/xilinx-versal/start/bspstart.c | 48 ++++ > .../xilinx-versal/start/bspstarthooks.c | 51 ++++ > .../aarch64/xilinx-versal/start/bspstartmmu.c | 77 ++++++ > bsps/include/dev/irq/arm-gic-regs.h | 6 +- > bsps/shared/dev/irq/arm-gicv3.c | 24 +- > spec/build/bsps/aarch64/a53/grp.yml | 2 + > spec/build/bsps/aarch64/a72/grp.yml | 2 + > spec/build/bsps/aarch64/optgtuseps.yml | 17 ++ > spec/build/bsps/aarch64/optgtusevirt.yml | 16 ++ > spec/build/bsps/aarch64/optisns.yml | 20 ++ > spec/build/bsps/aarch64/xilinx-versal/abi.yml | 22 ++ > .../aarch64/xilinx-versal/bspqemuilp32.yml | 19 ++ > .../aarch64/xilinx-versal/bspqemulp64.yml | 19 ++ > .../aarch64/xilinx-versal/bspvck190ilp32.yml | 19 ++ > .../aarch64/xilinx-versal/bspvck190lp64.yml | 19 ++ > spec/build/bsps/aarch64/xilinx-versal/grp.yml | 56 +++++ > .../bsps/aarch64/xilinx-versal/grp_qemu.yml | 18 ++ > .../bsps/aarch64/xilinx-versal/grp_vck190.yml | 18 ++ > .../aarch64/xilinx-versal/linkcmds_ilp32.yml | 74 ++++++ > .../aarch64/xilinx-versal/linkcmds_lp64.yml | 74 ++++++ > spec/build/bsps/aarch64/xilinx-versal/obj.yml | 44 ++++ > .../bsps/aarch64/xilinx-versal/optclkuart.yml | 20 ++ > .../aarch64/xilinx-versal/optconminor.yml | 16 ++ > .../bsps/aarch64/xilinx-versal/optloadoff.yml | 22 ++ > .../aarch64/xilinx-versal/optnocachelen.yml | 18 ++ > .../bsps/aarch64/xilinx-versal/optramlen.yml | 18 ++ > .../bsps/aarch64/xilinx-versal/optramori.yml | 22 ++ > .../bsps/aarch64/xilinx-versal/tstqemu.yml | 19 ++ > .../bsps/aarch64/xilinx-versal/tstvck190.yml | 19 ++ > spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 + > spec/build/bsps/optstartmon.yml | 16 ++ > 40 files changed, 1647 insertions(+), 7 deletions(-) > create mode 100644 bsps/aarch64/xilinx-versal/console/console.c > create mode 100644 bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c > create mode 100644 bsps/aarch64/xilinx-versal/include/bsp.h > create mode 100644 bsps/aarch64/xilinx-versal/include/bsp/irq.h > create mode 100644 > bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h > create mode 100644 > bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h > create mode 100644 bsps/aarch64/xilinx-versal/include/tm27.h > create mode 100644 bsps/aarch64/xilinx-versal/start/bspstart.c > create mode 100644 bsps/aarch64/xilinx-versal/start/bspstarthooks.c > create mode 100644 bsps/aarch64/xilinx-versal/start/bspstartmmu.c > create mode 100644 spec/build/bsps/aarch64/optgtuseps.yml > create mode 100644 spec/build/bsps/aarch64/optgtusevirt.yml > create mode 100644 spec/build/bsps/aarch64/optisns.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/abi.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/bspqemuilp32.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/bspqemulp64.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/bspvck190ilp32.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/bspvck190lp64.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/grp.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/grp_qemu.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/grp_vck190.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/obj.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/optclkuart.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/optconminor.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/optloadoff.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/optnocachelen.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/optramlen.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/optramori.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/tstqemu.yml > create mode 100644 spec/build/bsps/aarch64/xilinx-versal/tstvck190.yml > create mode 100644 spec/build/bsps/optstartmon.yml > > -- > 2.25.1 > > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
