--- user/bsps/aarch64/a72.rst | 35 +++++++++++++++++++++++++++++++++++ user/bsps/bsps-aarch64.rst | 1 + 2 files changed, 36 insertions(+) create mode 100644 user/bsps/aarch64/a72.rst
diff --git a/user/bsps/aarch64/a72.rst b/user/bsps/aarch64/a72.rst new file mode 100644 index 0000000..e8e4b3d --- /dev/null +++ b/user/bsps/aarch64/a72.rst @@ -0,0 +1,35 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +.. Copyright (C) 2020 On-Line Applications Research Corporation (OAR) + +.. _BSP_aarch64_qemu_a72_ilp32: +.. _BSP_aarch64_qemu_a72_lp64: + +Qemu A72 +======== + +This BSP supports two variants, `qemu_a72_ilp32` and `qemu_a72_lp64`. The basic +hardware initialization is performed by the BSP. These BSPs support the GICv3 +interrupt controller. + +Boot via ELF +------------ +The executable image is booted by Qemu in ELF format. + +Clock Driver +------------ + +The clock driver uses the `ARM Generic Timer`. + +Console Driver +-------------- + +The console driver supports the default Qemu emulated ARM PL011 PrimeCell UART. + +Running Executables +------------------- + +Executables generated by these BSPs can be run using the following command:: + +qemu-system-aarch64 -no-reboot -nographic -serial mon:stdio \ + -machine virt,gic-version=3 -cpu cortex-a72 -m 4096 -kernel example.exe diff --git a/user/bsps/bsps-aarch64.rst b/user/bsps/bsps-aarch64.rst index 0d4b23c..566a750 100644 --- a/user/bsps/bsps-aarch64.rst +++ b/user/bsps/bsps-aarch64.rst @@ -6,4 +6,5 @@ aarch64 (AArch64) ***************** .. include:: aarch64/a53.rst +.. include:: aarch64/a72.rst .. include:: aarch64/xilinx-zynqmp.rst -- 2.25.1 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
