---
bsps/aarch64/include/bsp/aarch64-sysregs.h | 291 ++++++++++++++++++
bsps/aarch64/shared/cache/cache.c | 168 +---------
spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 +
3 files changed, 293 insertions(+), 167 deletions(-)
create mode 100644 bsps/aarch64/include/bsp/aarch64-sysregs.h
diff --git a/bsps/aarch64/include/bsp/aarch64-sysregs.h
b/bsps/aarch64/include/bsp/aarch64-sysregs.h
new file mode 100644
index 0000000000..fca2728cd8
--- /dev/null
+++ b/bsps/aarch64/include/bsp/aarch64-sysregs.h
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup aarch64_start
+ *
+ * @brief These are the accessors and definitions of AArch64 system registers.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore <kinsey.mo...@oarcorp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_AARCH64_SHARED_AARCH64_SYSREGS_H
+#define LIBBSP_AARCH64_SHARED_AARCH64_SYSREGS_H
+
+#include <rtems.h>
+#include <bsp.h>
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+static inline uint64_t
+AArch64_get_ccsidr(void)
+{
+ uint64_t val;
+
+ __asm__ volatile (
+ "mrs %[val], CCSIDR_EL1\n"
+ : [val] "=&r" (val)
+ );
+
+ return val;
+}
+
+#define CCSIDR_NUMSETS(val) BSP_FLD64(val, 13, 27)
+#define CCSIDR_NUMSETS_GET(reg) BSP_FLD64GET(reg, 13, 27)
+#define CCSIDR_NUMSETS_SET(reg, val) BSP_FLD64SET(reg, val, 13, 27)
+#define CCSIDR_ASSOCIATIVITY(val) BSP_FLD64(val, 3, 12)
+#define CCSIDR_ASSOCIATIVITY_GET(reg) BSP_FLD64GET(reg, 3, 12)
+#define CCSIDR_ASSOCIATIVITY_SET(reg, val) BSP_FLD64SET(reg, val, 3, 12)
+/* line size == 1 << (GET(reg)+4): 0 -> (1 << 4) == 16 */
+#define CCSIDR_LINE_SIZE(val) BSP_FLD64(val, 0, 2)
+#define CCSIDR_LINE_SIZE_GET(reg) BSP_FLD64GET(reg, 0, 2)
+#define CCSIDR_LINE_SIZE_SET(reg, val) BSP_FLD64SET(reg, val, 0, 2)
+
+static inline uint64_t
+AArch64_ccsidr_get_line_power(uint64_t ccsidr)
+{
+ return CCSIDR_LINE_SIZE_GET(ccsidr) + 4;
+}
+
+static inline uint64_t
+AArch64_ccsidr_get_associativity(uint64_t ccsidr)
+{
+ return CCSIDR_ASSOCIATIVITY_GET(ccsidr) + 1;
+}
+
+static inline uint64_t
+AArch64_ccsidr_get_num_sets(uint64_t ccsidr)
+{
+ return CCSIDR_NUMSETS_GET(ccsidr) + 1;
+}
+
+static inline void
+AArch64_set_csselr(uint64_t val)
+{
+ __asm__ volatile (
+ "msr CSSELR_EL1, %[val]\n"
+ :
+ : [val] "r" (val)
+ );
+}
+#define CSSELR_TND BSP_BIT64(4)
+/* This field is level-1: L1 cache is 0, L2 cache is 1, etc */
+#define CSSELR_LEVEL(val) BSP_FLD64(val, 1, 3)
+#define CSSELR_LEVEL_GET(reg) BSP_FLD64GET(reg, 1, 3)
+#define CSSELR_LEVEL_SET(reg, val) BSP_FLD64SET(reg, val, 1, 3)
+#define CSSELR_IND BSP_BIT64(0)
+
+static inline uint64_t
+AArch64_get_clidr(void)
+{
+ uint64_t val;
+
+ __asm__ volatile (
+ "mrs %[val], CLIDR_EL1\n"
+ : [val] "=&r" (val)
+ );
+
+ return val;
+}
+
+#define CLIDR_LOC(val) BSP_FLD64(val, 24, 26)
+#define CLIDR_LOC_GET(reg) BSP_FLD64GET(reg, 24, 26)
+#define CLIDR_LOC_SET(reg, val) BSP_FLD64SET(reg, val, 24, 26)
+#define CLIDR_CTYPE7(val) BSP_FLD64(val, 18, 20)
+#define CLIDR_CTYPE7_GET(reg) BSP_FLD64GET(reg, 18, 20)
+#define CLIDR_CTYPE7_SET(reg, val) BSP_FLD64SET(reg, val, 18, 20)
+#define CLIDR_CTYPE6(val) BSP_FLD64(val, 15, 17)
+#define CLIDR_CTYPE6_GET(reg) BSP_FLD64GET(reg, 15, 17)
+#define CLIDR_CTYPE6_SET(reg, val) BSP_FLD64SET(reg, val, 15, 17)
+#define CLIDR_CTYPE5(val) BSP_FLD64(val, 12, 14)
+#define CLIDR_CTYPE5_GET(reg) BSP_FLD64GET(reg, 12, 14)
+#define CLIDR_CTYPE5_SET(reg, val) BSP_FLD64SET(reg, val, 12, 14)
+#define CLIDR_CTYPE4(val) BSP_FLD64(val, 9, 11)
+#define CLIDR_CTYPE4_GET(reg) BSP_FLD64GET(reg, 9, 11)
+#define CLIDR_CTYPE4_SET(reg, val) BSP_FLD64SET(reg, val, 9, 11)
+#define CLIDR_CTYPE3(val) BSP_FLD64(val, 6, 8)
+#define CLIDR_CTYPE3_GET(reg) BSP_FLD64GET(reg, 6, 8)
+#define CLIDR_CTYPE3_SET(reg, val) BSP_FLD64SET(reg, val, 6, 8)
+#define CLIDR_CTYPE2(val) BSP_FLD64(val, 3, 5)
+#define CLIDR_CTYPE2_GET(reg) BSP_FLD64GET(reg, 3, 5)
+#define CLIDR_CTYPE2_SET(reg, val) BSP_FLD64SET(reg, val, 3, 5)
+#define CLIDR_CTYPE1(val) BSP_FLD64(val, 0, 2)
+#define CLIDR_CTYPE1_GET(reg) BSP_FLD64GET(reg, 0, 2)
+#define CLIDR_CTYPE1_SET(reg, val) BSP_FLD64SET(reg, val, 0, 2)
+
+static inline uint64_t
+AArch64_get_sctlr(void)
+{
+ uint64_t val;
+
+ __asm__ volatile (
+ "mrs %[val], SCTLR_EL1\n"
+ : [val] "=&r" (val)
+ );
+
+ return val;
+}
+
+static inline void
+AArch64_set_sctlr(uint64_t val)
+{
+ __asm__ volatile (
+ "msr SCTLR_EL1, %[val]\n"
+ :
+ : [val] "r" (val)
+ );
+}
+
+#define SCTLR_TWEDEL(val) BSP_FLD64(val, 46, 49)
+#define SCTLR_TWEDEL_GET(reg) BSP_FLD64GET(reg, 46, 49)
+#define SCTLR_TWEDEL_SET(reg, val) BSP_FLD64SET(reg, val, 46, 49)
+#define SCTLR_TWEDEN BSP_BIT64(45)
+#define SCTLR_DSSBS BSP_BIT64(44)
+#define SCTLR_ATA BSP_BIT64(43)
+#define SCTLR_ATA0 BSP_BIT64(42)
+#define SCTLR_TCF(val) BSP_FLD64(val, 40, 41)
+#define SCTLR_TCF_GET(reg) BSP_FLD64GET(reg, 40, 41)
+#define SCTLR_TCF_SET(reg, val) BSP_FLD64SET(reg, val, 40, 41)
+#define SCTLR_TCF0(val) BSP_FLD64(val, 38, 39)
+#define SCTLR_TCF0_GET(reg) BSP_FLD64GET(reg, 38, 39)
+#define SCTLR_TCF0_SET(reg, val) BSP_FLD64SET(reg, val, 38, 39)
+#define SCTLR_ITFSB BSP_BIT64(37)
+#define SCTLR_BT1 BSP_BIT64(36)
+#define SCTLR_BT0 BSP_BIT64(35)
+#define SCTLR_ENIA BSP_BIT64(31)
+#define SCTLR_ENIB BSP_BIT64(30)
+#define SCTLR_LSMAOE BSP_BIT64(29)
+#define SCTLR_NTLSMD BSP_BIT64(28)
+#define SCTLR_ENDA BSP_BIT64(27)
+#define SCTLR_UCI BSP_BIT64(26)
+#define SCTLR_EE BSP_BIT64(25)
+#define SCTLR_E0E BSP_BIT64(24)
+#define SCTLR_SPAN BSP_BIT64(23)
+#define SCTLR_EIS BSP_BIT64(22)
+#define SCTLR_IESB BSP_BIT64(21)
+#define SCTLR_TSCXT BSP_BIT64(20)
+#define SCTLR_WXN BSP_BIT64(19)
+#define SCTLR_NTWE BSP_BIT64(18)
+#define SCTLR_NTWI BSP_BIT64(16)
+#define SCTLR_UCT BSP_BIT64(15)
+#define SCTLR_DZE BSP_BIT64(14)
+#define SCTLR_ENDB BSP_BIT64(13)
+#define SCTLR_I BSP_BIT64(12)
+#define SCTLR_EOS BSP_BIT64(11)
+#define SCTLR_ENRCTX BSP_BIT64(10)
+#define SCTLR_UMA BSP_BIT64(9)
+#define SCTLR_SED BSP_BIT64(8)
+#define SCTLR_ITD BSP_BIT64(7)
+#define SCTLR_NAA BSP_BIT64(6)
+#define SCTLR_CP15BEN BSP_BIT64(5)
+#define SCTLR_SA0 BSP_BIT64(4)
+#define SCTLR_SA BSP_BIT64(3)
+#define SCTLR_C BSP_BIT64(2)
+#define SCTLR_A BSP_BIT64(1)
+#define SCTLR_M BSP_BIT64(0)
+
+static inline void
+AArch64_set_ttbr0(uint64_t val)
+{
+ __asm__ volatile (
+ "msr TTBR0_EL1, %[val]\n"
+ :
+ : [val] "r" (val)
+ );
+}
+
+static inline void
+AArch64_set_tcr(uint64_t val)
+{
+ __asm__ volatile (
+ "msr TCR_EL1, %[val]\n"
+ :
+ : [val] "r" (val)
+ );
+}
+
+#define TCR_TG0(val) BSP_FLD64(val, 14, 15)
+#define TCR_TG0_GET(reg) BSP_FLD64GET(reg, 14, 15)
+#define TCR_TG0_SET(reg, val) BSP_FLD64SET(reg, val, 14, 15)
+#define TCR_SH0(val) BSP_FLD64(val, 12, 13)
+#define TCR_SH0_GET(reg) BSP_FLD64GET(reg, 12, 13)
+#define TCR_SH0_SET(reg, val) BSP_FLD64SET(reg, val, 12, 13)
+#define TCR_ORGN0(val) BSP_FLD64(val, 10, 11)
+#define TCR_ORGN0_GET(reg) BSP_FLD64GET(reg, 10, 11)
+#define TCR_ORGN0_SET(reg, val) BSP_FLD64SET(reg, val, 10, 11)
+#define TCR_IRGN0(val) BSP_FLD64(val, 8, 9)
+#define TCR_IRGN0_GET(reg) BSP_FLD64GET(reg, 8, 9)
+#define TCR_IRGN0_SET(reg, val) BSP_FLD64SET(reg, val, 8, 9)
+#define TCR_EPD0 BSP_BIT64(7)
+#define TCR_T0SZ(val) BSP_FLD64(val, 0, 5)
+#define TCR_T0SZ_GET(reg) BSP_FLD64GET(reg, 0, 5)
+#define TCR_T0SZ_SET(reg, val) BSP_FLD64SET(reg, val, 0, 5)
+
+static inline void
+AArch64_set_mair(uint64_t val)
+{
+ __asm__ volatile (
+ "msr MAIR_EL1, %[val]\n"
+ :
+ : [val] "r" (val)
+ );
+}
+
+#define MAIR_ATTR7(val) BSP_FLD64(val, 56, 63)
+#define MAIR_ATTR7_GET(reg) BSP_FLD64GET(reg, 56, 63)
+#define MAIR_ATTR7_SET(reg, val) BSP_FLD64SET(reg, val, 56, 63)
+#define MAIR_ATTR6(val) BSP_FLD64(val, 48, 55)
+#define MAIR_ATTR6_GET(reg) BSP_FLD64GET(reg, 48, 55)
+#define MAIR_ATTR6_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
+#define MAIR_ATTR5(val) BSP_FLD64(val, 40, 47)
+#define MAIR_ATTR5_GET(reg) BSP_FLD64GET(reg, 40, 47)
+#define MAIR_ATTR5_SET(reg, val) BSP_FLD64SET(reg, val, 40, 47)
+#define MAIR_ATTR4(val) BSP_FLD64(val, 32, 39)
+#define MAIR_ATTR4_GET(reg) BSP_FLD64GET(reg, 32, 39)
+#define MAIR_ATTR4_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
+#define MAIR_ATTR3(val) BSP_FLD64(val, 24, 31)
+#define MAIR_ATTR3_GET(reg) BSP_FLD64GET(reg, 24, 31)
+#define MAIR_ATTR3_SET(reg, val) BSP_FLD64SET(reg, val, 24, 31)
+#define MAIR_ATTR2(val) BSP_FLD64(val, 16, 23)
+#define MAIR_ATTR2_GET(reg) BSP_FLD64GET(reg, 16, 23)
+#define MAIR_ATTR2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
+#define MAIR_ATTR1(val) BSP_FLD64(val, 8, 15)
+#define MAIR_ATTR1_GET(reg) BSP_FLD64GET(reg, 8, 15)
+#define MAIR_ATTR1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
+#define MAIR_ATTR0(val) BSP_FLD64(val, 0, 7)
+#define MAIR_ATTR0_GET(reg) BSP_FLD64GET(reg, 0, 7)
+#define MAIR_ATTR0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_AARCH64_SHARED_AARCH64_SYSREGS_H */
diff --git a/bsps/aarch64/shared/cache/cache.c
b/bsps/aarch64/shared/cache/cache.c
index d7ea33206f..9bdbe88c92 100644
--- a/bsps/aarch64/shared/cache/cache.c
+++ b/bsps/aarch64/shared/cache/cache.c
@@ -37,6 +37,7 @@
#include <rtems.h>
#include <bsp.h>
#include <bsp/utility.h>
+#include <bsp/aarch64-sysregs.h>
#define AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ((size_t)64)
#define AARCH64_CACHE_L1_DATA_LINE_MASK \
@@ -175,64 +176,6 @@ static inline void _CPU_cache_unfreeze_instruction(void)
/* TODO */
}
-static inline uint64_t
-AArch64_get_ccsidr(void)
-{
- uint64_t val;
-
- __asm__ volatile (
- "mrs %[val], CCSIDR_EL1\n"
- : [val] "=&r" (val)
- );
-
- return val;
-}
-
-#define CCSIDR_NUMSETS(val) BSP_FLD64(val, 13, 27)
-#define CCSIDR_NUMSETS_GET(reg) BSP_FLD64GET(reg, 13, 27)
-#define CCSIDR_NUMSETS_SET(reg, val) BSP_FLD64SET(reg, val, 13, 27)
-#define CCSIDR_ASSOCIATIVITY(val) BSP_FLD64(val, 3, 12)
-#define CCSIDR_ASSOCIATIVITY_GET(reg) BSP_FLD64GET(reg, 3, 12)
-#define CCSIDR_ASSOCIATIVITY_SET(reg, val) BSP_FLD64SET(reg, val, 3, 12)
-/* line size == 1 << (GET(reg)+4): 0 -> (1 << 4) == 16 */
-#define CCSIDR_LINE_SIZE(val) BSP_FLD64(val, 0, 2)
-#define CCSIDR_LINE_SIZE_GET(reg) BSP_FLD64GET(reg, 0, 2)
-#define CCSIDR_LINE_SIZE_SET(reg, val) BSP_FLD64SET(reg, val, 0, 2)
-
-static inline uint64_t
-AArch64_ccsidr_get_line_power(uint64_t ccsidr)
-{
- return CCSIDR_LINE_SIZE_GET(ccsidr) + 4;
-}
-
-static inline uint64_t
-AArch64_ccsidr_get_associativity(uint64_t ccsidr)
-{
- return CCSIDR_ASSOCIATIVITY_GET(ccsidr) + 1;
-}
-
-static inline uint64_t
-AArch64_ccsidr_get_num_sets(uint64_t ccsidr)
-{
- return CCSIDR_NUMSETS_GET(ccsidr) + 1;
-}
-
-static inline void
-AArch64_set_csselr(uint64_t val)
-{
- __asm__ volatile (
- "msr CSSELR_EL1, %[val]\n"
- :
- : [val] "r" (val)
- );
-}
-#define CSSELR_TND BSP_BIT64(4)
-/* This field is level-1: L1 cache is 0, L2 cache is 1, etc */
-#define CSSELR_LEVEL(val) BSP_FLD64(val, 1, 3)
-#define CSSELR_LEVEL_GET(reg) BSP_FLD64GET(reg, 1, 3)
-#define CSSELR_LEVEL_SET(reg, val) BSP_FLD64SET(reg, val, 1, 3)
-#define CSSELR_IND BSP_BIT64(0)
-
static inline uint64_t AArch64_get_ccsidr_for_level(uint64_t val)
{
AArch64_set_csselr(val);
@@ -272,44 +215,6 @@ static inline void AArch64_data_cache_clean_level(uint64_t
level)
}
}
-static inline uint64_t
-AArch64_get_clidr(void)
-{
- uint64_t val;
-
- __asm__ volatile (
- "mrs %[val], CLIDR_EL1\n"
- : [val] "=&r" (val)
- );
-
- return val;
-}
-
-#define CLIDR_LOC(val) BSP_FLD64(val, 24, 26)
-#define CLIDR_LOC_GET(reg) BSP_FLD64GET(reg, 24, 26)
-#define CLIDR_LOC_SET(reg, val) BSP_FLD64SET(reg, val, 24, 26)
-#define CLIDR_CTYPE7(val) BSP_FLD64(val, 18, 20)
-#define CLIDR_CTYPE7_GET(reg) BSP_FLD64GET(reg, 18, 20)
-#define CLIDR_CTYPE7_SET(reg, val) BSP_FLD64SET(reg, val, 18, 20)
-#define CLIDR_CTYPE6(val) BSP_FLD64(val, 15, 17)
-#define CLIDR_CTYPE6_GET(reg) BSP_FLD64GET(reg, 15, 17)
-#define CLIDR_CTYPE6_SET(reg, val) BSP_FLD64SET(reg, val, 15, 17)
-#define CLIDR_CTYPE5(val) BSP_FLD64(val, 12, 14)
-#define CLIDR_CTYPE5_GET(reg) BSP_FLD64GET(reg, 12, 14)
-#define CLIDR_CTYPE5_SET(reg, val) BSP_FLD64SET(reg, val, 12, 14)
-#define CLIDR_CTYPE4(val) BSP_FLD64(val, 9, 11)
-#define CLIDR_CTYPE4_GET(reg) BSP_FLD64GET(reg, 9, 11)
-#define CLIDR_CTYPE4_SET(reg, val) BSP_FLD64SET(reg, val, 9, 11)
-#define CLIDR_CTYPE3(val) BSP_FLD64(val, 6, 8)
-#define CLIDR_CTYPE3_GET(reg) BSP_FLD64GET(reg, 6, 8)
-#define CLIDR_CTYPE3_SET(reg, val) BSP_FLD64SET(reg, val, 6, 8)
-#define CLIDR_CTYPE2(val) BSP_FLD64(val, 3, 5)
-#define CLIDR_CTYPE2_GET(reg) BSP_FLD64GET(reg, 3, 5)
-#define CLIDR_CTYPE2_SET(reg, val) BSP_FLD64SET(reg, val, 3, 5)
-#define CLIDR_CTYPE1(val) BSP_FLD64(val, 0, 2)
-#define CLIDR_CTYPE1_GET(reg) BSP_FLD64GET(reg, 0, 2)
-#define CLIDR_CTYPE1_SET(reg, val) BSP_FLD64SET(reg, val, 0, 2)
-
static inline
uint64_t AArch64_clidr_get_cache_type(uint64_t clidr, uint64_t level)
{
@@ -416,77 +321,6 @@ static inline void _CPU_cache_invalidate_entire_data(void)
AArch64_data_cache_invalidate_all_levels();
}
-static inline uint64_t
-AArch64_get_sctlr(void)
-{
- uint64_t val;
-
- __asm__ volatile (
- "mrs %[val], SCTLR_EL1\n"
- : [val] "=&r" (val)
- );
-
- return val;
-}
-
-static inline void
-AArch64_set_sctlr(uint64_t val)
-{
- __asm__ volatile (
- "msr SCTLR_EL1, %[val]\n"
- :
- : [val] "r" (val)
- );
-}
-
-#define SCTLR_TWEDEL(val) BSP_FLD64(val, 46, 49)
-#define SCTLR_TWEDEL_GET(reg) BSP_FLD64GET(reg, 46, 49)
-#define SCTLR_TWEDEL_SET(reg, val) BSP_FLD64SET(reg, val, 46, 49)
-#define SCTLR_TWEDEN BSP_BIT64(45)
-#define SCTLR_DSSBS BSP_BIT64(44)
-#define SCTLR_ATA BSP_BIT64(43)
-#define SCTLR_ATA0 BSP_BIT64(42)
-#define SCTLR_TCF(val) BSP_FLD64(val, 40, 41)
-#define SCTLR_TCF_GET(reg) BSP_FLD64GET(reg, 40, 41)
-#define SCTLR_TCF_SET(reg, val) BSP_FLD64SET(reg, val, 40, 41)
-#define SCTLR_TCF0(val) BSP_FLD64(val, 38, 39)
-#define SCTLR_TCF0_GET(reg) BSP_FLD64GET(reg, 38, 39)
-#define SCTLR_TCF0_SET(reg, val) BSP_FLD64SET(reg, val, 38, 39)
-#define SCTLR_ITFSB BSP_BIT64(37)
-#define SCTLR_BT1 BSP_BIT64(36)
-#define SCTLR_BT0 BSP_BIT64(35)
-#define SCTLR_ENIA BSP_BIT64(31)
-#define SCTLR_ENIB BSP_BIT64(30)
-#define SCTLR_LSMAOE BSP_BIT64(29)
-#define SCTLR_NTLSMD BSP_BIT64(28)
-#define SCTLR_ENDA BSP_BIT64(27)
-#define SCTLR_UCI BSP_BIT64(26)
-#define SCTLR_EE BSP_BIT64(25)
-#define SCTLR_E0E BSP_BIT64(24)
-#define SCTLR_SPAN BSP_BIT64(23)
-#define SCTLR_EIS BSP_BIT64(22)
-#define SCTLR_IESB BSP_BIT64(21)
-#define SCTLR_TSCXT BSP_BIT64(20)
-#define SCTLR_WXN BSP_BIT64(19)
-#define SCTLR_NTWE BSP_BIT64(18)
-#define SCTLR_NTWI BSP_BIT64(16)
-#define SCTLR_UCT BSP_BIT64(15)
-#define SCTLR_DZE BSP_BIT64(14)
-#define SCTLR_ENDB BSP_BIT64(13)
-#define SCTLR_I BSP_BIT64(12)
-#define SCTLR_EOS BSP_BIT64(11)
-#define SCTLR_ENRCTX BSP_BIT64(10)
-#define SCTLR_UMA BSP_BIT64(9)
-#define SCTLR_SED BSP_BIT64(8)
-#define SCTLR_ITD BSP_BIT64(7)
-#define SCTLR_NAA BSP_BIT64(6)
-#define SCTLR_CP15BEN BSP_BIT64(5)
-#define SCTLR_SA0 BSP_BIT64(4)
-#define SCTLR_SA BSP_BIT64(3)
-#define SCTLR_C BSP_BIT64(2)
-#define SCTLR_A BSP_BIT64(1)
-#define SCTLR_M BSP_BIT64(0)
-
static inline void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
index a4a4c74333..e7026da892 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml
@@ -15,6 +15,7 @@ install:
- destination: ${BSP_INCLUDEDIR}/bsp
source:
- bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
+ - bsps/aarch64/include/bsp/aarch64-sysregs.h
links: []
source:
- bsps/aarch64/shared/cache/cache.c
--
2.20.1
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