ok
On Fri, Apr 9, 2021 at 4:35 PM Kinsey Moore <kinsey.mo...@oarcorp.com> wrote:
>
> The _CPU_ISR_Is_enabled() function operates on ISR cookies and so must
> mask off the appropriate status bits. This also fixes the naming of the
> parameters of the _CPU_ISR_* functions to indicate use of ISR cookies
> instead of interrupt enable/disable levels.
> ---
> .../cpu/aarch64/include/rtems/score/cpu.h | 26 +++++++++----------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> index 707dce1d55..eb2206ffc7 100644
> --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
> @@ -210,33 +210,33 @@ uint64_t _CPU_ISR_Get_level( void );
>
> #if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
> uint64_t AArch64_interrupt_disable( void );
> -void AArch64_interrupt_enable( uint64_t level );
> -void AArch64_interrupt_flash( uint64_t level );
> +void AArch64_interrupt_enable( uint64_t isr_cookie );
> +void AArch64_interrupt_flash( uint64_t isr_cookie );
> #else
> static inline uint64_t AArch64_interrupt_disable( void )
> {
> - uint64_t level;
> + uint64_t isr_cookie;
>
> __asm__ volatile (
> - "mrs %[level], DAIF\n"
> + "mrs %[isr_cookie], DAIF\n"
> "msr DAIFSet, #0x2\n"
> - : [level] "=&r" (level)
> + : [isr_cookie] "=&r" (isr_cookie)
> );
>
> - return level;
> + return isr_cookie;
> }
>
> -static inline void AArch64_interrupt_enable( uint64_t level )
> +static inline void AArch64_interrupt_enable( uint64_t isr_cookie )
> {
> __asm__ volatile (
> - "msr DAIF, %[level]\n"
> - : : [level] "r" (level)
> + "msr DAIF, %[isr_cookie]\n"
> + : : [isr_cookie] "r" (isr_cookie)
> );
> }
>
> -static inline void AArch64_interrupt_flash( uint64_t level )
> +static inline void AArch64_interrupt_flash( uint64_t isr_cookie )
> {
> - AArch64_interrupt_enable(level);
> + AArch64_interrupt_enable(isr_cookie);
> AArch64_interrupt_disable();
> }
> #endif /* !AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE */
> @@ -252,9 +252,9 @@ static inline void AArch64_interrupt_flash( uint64_t
> level )
> #define _CPU_ISR_Flash( _isr_cookie ) \
> AArch64_interrupt_flash( _isr_cookie )
>
> -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t level )
> +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t isr_cookie )
> {
> - return level == 0;
> + return ( isr_cookie & AARCH64_PSTATE_I ) == 0;
> }
>
> void _CPU_Context_Initialize(
> --
> 2.20.1
>
> _______________________________________________
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> devel@rtems.org
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