On Mon, Mar 22, 2021 at 12:53 PM Alex White <alex.wh...@oarcorp.com> wrote:
> ---
> .../aarch64/aarch64-exception-frame-print.c | 106 +++++++++++++++++-
> 1 file changed, 102 insertions(+), 4 deletions(-)
>
> diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
> b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
> index 59b5d06032..b22d99a0ca 100644
> --- a/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
> +++ b/cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
> @@ -45,8 +45,91 @@
> #include <inttypes.h>
>
> #include <rtems/score/cpu.h>
> +#include <rtems/score/io.h>
> #include <rtems/bspIo.h>
>
> +static const char* _exception_class_to_string( uint16_t exception_class );
> +
> +static void _binary_sprintf(
> + char *s,
> + size_t maxlen,
> + uint32_t num_bits,
> + uint32_t value
> +);
> +
> +static const char* _exception_class_to_string( uint16_t exception_class )
> +{
> + switch (exception_class)
> + {
> + case 0b000001: return "Trapped WFI or WFE instruction";
> + case 0b000011: return "Trapped MCR or MRC access with (coproc==0b1111)";
> + case 0b000100: return "Trapped MCRR or MRRC access with
> (coproc==0b1111)";
> + case 0b000101: return "Trapped MCR or MRC access with (coproc==0b1110)";
> + case 0b000110: return "Trapped LDC or STC access";
> + case 0b001100: return "Trapped MRRC access with (coproc==0b1110)";
> + case 0b001110: return "Illegal Execution state";
> + case 0b011000: return "Trapped MSR, MRS, or System instruction";
> + case 0b100000: return "Instruction Abort from a lower Exception level";
> + case 0b100001: return "Instruction Abort taken without a change in
> Exception "
> + "level";
> + case 0b100010: return "PC alignment fault";
> + case 0b100100: return "Data Abort from a lower Exception level";
> + case 0b100101: return "Data Abort taken without a change in Exception
> level";
> + case 0b100110: return "SP alignment fault";
> + case 0b110000: return "Breakpoint exception from a lower Exception
> level";
> + case 0b110001: return "Breakpoint exception taken without a change in "
> + "Exception level";
> + case 0b110010: return "Software Step exception from a lower Exception
> level";
> + case 0b110011: return "Software Step exception taken without a change
> in "
> + "Exception level";
> + case 0b110100: return "Watchpoint exception from a lower Exception
> level";
> + case 0b110101: return "Watchpoint exception taken without a change in "
> + "Exception level";
> + case 0b111000: return "BKPT instruction execution in AArch32 state";
> + case 0b111100: return "BRK instruction execution in AArch64 state";
>
Before someone else asks...
(1) Are binary constants standard C? The stackover flow discussion I found
says they are a GNU extension which puts them off-limits.
(2). These appear to be 6 bits and there is nothing ensuring only those six
bits are set before the switch. Is there a chance other bits could be set
messing up this switch?
> + default: return "Unknown";
> + }
> +}
> +
> +typedef struct {
> + char *s;
> + size_t n;
> +} string_context;
> +
> +static void put_char(int c, void *arg)
> +{
> + string_context *sctx = arg;
> + size_t n = sctx->n;
> +
> + if (n > 0) {
> + char *s = sctx->s;
> + *s = (char)c;
> + sctx->s = s + 1;
> + sctx->n = n - 1;
> + }
> +}
> +
> +static void _binary_sprintf(
> + char *s,
> + size_t maxlen,
> + uint32_t num_bits,
> + uint32_t value
> +)
> +{
> + string_context sctx = {
> + .s = s,
> + .n = maxlen
> + };
> + uint32_t mask = 1<<(num_bits-1);
> + int cx = 0;
> +
> + while ( mask != 0 ) {
> + cx += _IO_Printf(put_char, &sctx, "%d", (value & mask ? 1 : 0));
> + //cx += snprintf(s + cx, maxlen - cx, "%d", (value&mask ? 1 : 0));
>
Commented out.
> + mask >>= 1;
> + }
> +}
> +
> void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
> {
> printk(
> @@ -68,8 +151,7 @@ void _CPU_Exception_frame_print( const
> CPU_Exception_frame *frame )
> "X14 = 0x%016" PRIx64 " SP = 0x%016" PRIxPTR "\n"
> "X15 = 0x%016" PRIx64 " PC = 0x%016" PRIxPTR "\n"
> "X16 = 0x%016" PRIx64 " DAIF = 0x%016" PRIx64 "\n"
> - "VEC = 0x%016" PRIxPTR " CPSR = 0x%016" PRIx64 "\n"
> - "ESR = 0x%016" PRIx64 " FAR = 0x%016" PRIx64 "\n",
> + "VEC = 0x%016" PRIxPTR " CPSR = 0x%016" PRIx64 "\n",
> frame->register_x0, frame->register_x17,
> frame->register_x1, frame->register_x18,
> frame->register_x2, frame->register_x19,
> @@ -87,10 +169,26 @@ void _CPU_Exception_frame_print( const
> CPU_Exception_frame *frame )
> frame->register_x14, (intptr_t)frame->register_sp,
> frame->register_x15, (intptr_t)frame->register_pc,
> frame->register_x16, frame->register_daif,
> - (intptr_t) frame->vector, frame->register_cpsr,
> - frame->register_syndrome, frame->register_fault_address
> + (intptr_t) frame->vector, frame->register_cpsr
> );
>
> + uint32_t ec = (frame->register_syndrome >> 26) & 0x3f;
> + uint32_t il = (frame->register_syndrome >> 25) & 0x1;
> + uint32_t iss = frame->register_syndrome & 0x1ffffff;
> + char ec_str[7] = {0};
> + char iss_str[26] = {0};
> +
> + _binary_sprintf(ec_str, 7, 6, ec);
> + _binary_sprintf(iss_str, 26, 25, iss);
> +
> + printk(
> + "ESR = EC: 0b%s" " IL: 0b%d" " ISS: 0b%s" "\n"
> + " %s\n",
> + ec_str, il, iss_str, _exception_class_to_string(ec)
> + );
> +
> + printk( "FAR = 0x%016" PRIx64 "\n", frame->register_fault_address );
> +
> const uint128_t *qx = &frame->register_q0;
> int i;
>
> --
> 2.27.0
>
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