On 16/02/2021 03:02, chr...@rtems.org wrote:
+/*
+ * Values for the bus space tag, not to be used directly by MI code.
+ */
+#define BSP_BUS_SPACE_IO 0 /* space is i/o space */
+#define BSP_BUS_SPACE_MEM 1 /* space is mem space */
+
+/*
+ * BSP PCI Support
+ *
+ * The RTEMS Nexus bus support can optionaly support PCI spaces that
+ * mapped to BSP speciic address spaces. Add the following define to
+ * the BSP header file to enable this support:
+ *
+ * #define BSP_HAS_PCI
+ *
+ * If enabled a BSP must the following IO region calls:
+ *
+ * inb : read 8 bits
+ * outb : write 8 bits
+ * inw : read 16 bits
+ * outw : write 16 bits
+ * inl : read 32 bits
+ * outl : write 32 bits
+ *
+ * The BSP needs to provide the DRAM address space offset
+ * PCI_DRAM_OFFSET. This is the base address of the DRAM as seen by a
+ * PCI master.
Why is it not possible to account for this offset in the
bus_space_handle_t bsh? I thought the purpose of the bus_space_tag_t bst
was to select different instructions to access the memory space. The
generic file is for systems with memory mapped access only.
+ *
+ * i386 BSPs have a special bus.h file and do not use this file.
+ */
+#include <bsp.h>
+
/*
* Bus address alignment.
*/
@@ -144,6 +180,7 @@
/*
* Bus access.
*/
+#define BUS_SPACE_INVALID_DATA (~0)
#define BUS_SPACE_UNRESTRICTED (~0U)
/*
@@ -228,29 +265,52 @@ bus_space_barrier(bus_space_tag_t bst __unused,
bus_space_handle_t bsh, bus_size
* data is returned.
*/
static __inline uint8_t
-bus_space_read_1(bus_space_tag_t bst __unused, bus_space_handle_t bsh,
bus_size_t ofs)
+bus_space_read_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs)
{
+ if (bst == BSP_BUS_SPACE_IO) {
+#ifdef BSP_HAS_PCI
+ return inb(bsh + ofs);
+#else
+ return BUS_SPACE_INVALID_DATA;
+#endif
+ }
This adds a conditional to all memory mapped generic architectures. From
my point of view this is a potential code size and performance
regression. It also includes <bsp.h> and thus <rtems.h> in a file which
is included all over the place.
uint8_t __volatile *bsp = (uint8_t __volatile *)(bsh + ofs);
return (*bsp);
}
--
embedded brains GmbH
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler
Unsere Datenschutzerklärung finden Sie hier:
https://embedded-brains.de/datenschutzerklaerung/
_______________________________________________
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel